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Commit 5e3165d1 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/enumeration' 

  - neaten pci=earlydump output (Andy Shevchenko)

  - avoid errors when extended config space inaccessible (Gilles Buloz)

  - prevent sysfs disable of device while driver attached (Christoph
    Hellwig)

  - use core interface to report PCIe link properties in bnx2x, bnxt_en,
    cxgb4, ixgbe (Bjorn Helgaas)

  - remove unused pcie_get_minimum_link() (Bjorn Helgaas)

* pci/enumeration:
  PCI: Remove unused pcie_get_minimum_link()
  ixgbe: Report PCIe link properties with pcie_print_link_status()
  cxgb4: Report PCIe link properties with pcie_print_link_status()
  bnxt_en: Report PCIe link properties with pcie_print_link_status()
  bnx2x: Report PCIe link properties with pcie_print_link_status()
  PCI: Prevent sysfs disable of device while driver is attached
  PCI: Check whether bridges allow access to extended config space
  x86/PCI: Make pci=earlydump output neat
parents 8e069da2 e5b1db01

arch/x86/pci/early.c

+5 −14
Original line number Diff line number Diff line
@@ -59,24 +59,15 @@ int early_pci_allowed(void) 


void early_dump_pci_device(u8 bus, u8 slot, u8 func)

{

	u32 value[256 / 4];

	int i;

	int j;

	u32 val;



	printk(KERN_INFO "pci 0000:%02x:%02x.%d config space:",

	       bus, slot, func);

	pr_info("pci 0000:%02x:%02x.%d config space:\n", bus, slot, func);



	for (i = 0; i < 256; i += 4) {

		if (!(i & 0x0f))

			printk("\n  %02x:",i);

	for (i = 0; i < 256; i += 4)

		value[i / 4] = read_pci_config(bus, slot, func, i);



		val = read_pci_config(bus, slot, func, i);

		for (j = 0; j < 4; j++) {

			printk(" %02x", val & 0xff);

			val >>= 8;

		}

	}

	printk("\n");

	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, value, 256, false);

}



void early_dump_pci_devices(void)

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+6 −17
Original line number Diff line number Diff line
@@ -13922,8 +13922,6 @@ static int bnx2x_init_one(struct pci_dev *pdev, 
{

	struct net_device *dev = NULL;

	struct bnx2x *bp;

	enum pcie_link_width pcie_width;

	enum pci_bus_speed pcie_speed;

	int rc, max_non_def_sbs;

	int rx_count, tx_count, rss_count, doorbell_size;

	int max_cos_est;
@@ -14091,21 +14089,12 @@ static int bnx2x_init_one(struct pci_dev *pdev, 
		dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);

		rtnl_unlock();

	}

	if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||

	    pcie_speed == PCI_SPEED_UNKNOWN ||

	    pcie_width == PCIE_LNK_WIDTH_UNKNOWN)

		BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");

	else

	BNX2X_DEV_INFO(

		       "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",

	       "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",

	       board_info[ent->driver_data].name,

	       (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),

		       pcie_width,

		       pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :

		       pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :

		       pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :

		       "Unknown",

	       dev->base_addr, bp->pdev->irq, dev->dev_addr);

	pcie_print_link_status(bp->pdev);



	bnx2x_register_phc(bp);

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+1 −18
Original line number Diff line number Diff line
@@ -8621,22 +8621,6 @@ static int bnxt_init_mac_addr(struct bnxt *bp) 
	return rc;

}



static void bnxt_parse_log_pcie_link(struct bnxt *bp)

{

	enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;

	enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;



	if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||

	    speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)

		netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");

	else

		netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",

			    speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :

			    speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :

			    speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :

			    "Unknown", width);

}



static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)

{

	static int version_printed;
@@ -8851,8 +8835,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	netdev_info(dev, "%s found at mem %lx, node addr %pM\n",

		    board_info[ent->driver_data].name,

		    (long)pci_resource_start(pdev, 0), dev->dev_addr);



	bnxt_parse_log_pcie_link(bp);

	pcie_print_link_status(pdev);



	return 0;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+1 −74
Original line number Diff line number Diff line
@@ -5042,79 +5042,6 @@ static int init_rss(struct adapter *adap) 
	return 0;

}



static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,

					enum pci_bus_speed *speed,

					enum pcie_link_width *width)

{

	u32 lnkcap1, lnkcap2;

	int err1, err2;



#define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */



	*speed = PCI_SPEED_UNKNOWN;

	*width = PCIE_LNK_WIDTH_UNKNOWN;



	err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,

					  &lnkcap1);

	err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,

					  &lnkcap2);

	if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */

		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)

			*speed = PCIE_SPEED_8_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)

			*speed = PCIE_SPEED_5_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)

			*speed = PCIE_SPEED_2_5GT;

	}

	if (!err1) {

		*width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;

		if (!lnkcap2) { /* pre-r3.0 */

			if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)

				*speed = PCIE_SPEED_5_0GT;

			else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)

				*speed = PCIE_SPEED_2_5GT;

		}

	}



	if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)

		return err1 ? err1 : err2 ? err2 : -EINVAL;

	return 0;

}



static void cxgb4_check_pcie_caps(struct adapter *adap)

{

	enum pcie_link_width width, width_cap;

	enum pci_bus_speed speed, speed_cap;



#define PCIE_SPEED_STR(speed) \

	(speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \

	 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \

	 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \

	 "Unknown")



	if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {

		dev_warn(adap->pdev_dev,

			 "Unable to determine PCIe device BW capabilities\n");

		return;

	}



	if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||

	    speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {

		dev_warn(adap->pdev_dev,

			 "Unable to determine PCI Express bandwidth.\n");

		return;

	}



	dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",

		 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));

	dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",

		 width, width_cap);

	if (speed < speed_cap || width < width_cap)

		dev_info(adap->pdev_dev,

			 "A slot with more lanes and/or higher speed is "

			 "suggested for optimal performance.\n");

}



/* Dump basic information about the adapter */

static void print_adapter_info(struct adapter *adapter)

{
@@ -5750,7 +5677,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	}



	/* check for PCI Express bandwidth capabiltites */

	cxgb4_check_pcie_caps(adapter);

	pcie_print_link_status(pdev);



	err = init_rss(adapter);

	if (err)

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

+1 −46
Original line number Diff line number Diff line
@@ -270,9 +270,6 @@ static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 
				     int expected_gts)

{

	struct ixgbe_hw *hw = &adapter->hw;

	int max_gts = 0;

	enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;

	enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;

	struct pci_dev *pdev;



	/* Some devices are not connected over PCIe and thus do not negotiate
@@ -288,49 +285,7 @@ static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 
	else

		pdev = adapter->pdev;



	if (pcie_get_minimum_link(pdev, &speed, &width) ||

	    speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {

		e_dev_warn("Unable to determine PCI Express bandwidth.\n");

		return;

	}



	switch (speed) {

	case PCIE_SPEED_2_5GT:

		/* 8b/10b encoding reduces max throughput by 20% */

		max_gts = 2 * width;

		break;

	case PCIE_SPEED_5_0GT:

		/* 8b/10b encoding reduces max throughput by 20% */

		max_gts = 4 * width;

		break;

	case PCIE_SPEED_8_0GT:

		/* 128b/130b encoding reduces throughput by less than 2% */

		max_gts = 8 * width;

		break;

	default:

		e_dev_warn("Unable to determine PCI Express bandwidth.\n");

		return;

	}



	e_dev_info("PCI Express bandwidth of %dGT/s available\n",

		   max_gts);

	e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",

		   (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :

		    speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :

		    speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :

		    "Unknown"),

		   width,

		   (speed == PCIE_SPEED_2_5GT ? "20%" :

		    speed == PCIE_SPEED_5_0GT ? "20%" :

		    speed == PCIE_SPEED_8_0GT ? "<2%" :

		    "Unknown"));



	if (max_gts < expected_gts) {

		e_dev_warn("This is not sufficient for optimal performance of this card.\n");

		e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",

			expected_gts);

		e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");

	}

	pcie_print_link_status(pdev);

}



static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)