Merge tag 'spi-nor/for-4.11-v2' of git://github.com/spi-nor/linux

* Aspeed Firmware Memory controller

* Aspeed SPI Flash Memory Controller

The Firmware Memory Controller in the Aspeed AST2500 SoC supports

three chip selects, two of which are always of SPI type and the third

can be SPI or NOR type flash. These bindings only describe SPI.

The two SPI flash memory controllers in the AST2500 each support two

chip selects.

Required properties:

  - compatible : Should be one of

	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller

	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller

	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller

	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers

  - reg : the first contains the control register location and length,

          the second contains the memory window mapping address and length

  - #address-cells : must be 1 corresponding to chip select child binding

  - #size-cells : must be 0 corresponding to chip select child binding

Optional properties:

  - interrupts : Should contain the interrupt for the dma device if an

    FMC

The child nodes are the SPI flash modules which must have a compatible

property as specified in bindings/mtd/jedec,spi-nor.txt

Optionally, the child node can contain properties for SPI mode (may be

ignored):

  - spi-max-frequency - max frequency of spi bus

Example:

fmc: fmc@1e620000 {

	compatible = "aspeed,ast2500-fmc";

	reg = < 0x1e620000 0x94

		0x20000000 0x02000000 >;

	#address-cells = <1>;

	#size-cells = <0>;

	interrupts = <19>;

	flash@0 {

		reg = < 0 >;

		compatible = "jedec,spi-nor";

		/* spi-max-frequency = <>; */

		/* m25p,fast-read; */

		#address-cells = <1>;

		#size-cells = <1>;

	};

};

                 at25df641

                 at26df081a

                 mr25h256

                 mr25h10

                 mr25h40

                 mx25l4005a

                 mx25l1606e

                 mx25l6405d

* Serial NOR flash controller for MTK MT81xx (and similar)

Required properties:

- compatible: 	  should be "mediatek,mt8173-nor";

- compatible: 	  The possible values are:

		  "mediatek,mt2701-nor"

		  "mediatek,mt7623-nor"

		  "mediatek,mt8173-nor"

		  For mt8173, compatible should be "mediatek,mt8173-nor".

		  For every other SoC, should contain both the SoC-specific compatible string

		  and "mediatek,mt8173-nor".

- reg: 		  physical base address and length of the controller's register

- clocks: 	  the phandle of the clocks needed by the nor controller

- clock-names: 	  the names of the clocks

Upgrading BIOS using intel-spi

------------------------------

Many Intel CPUs like Baytrail and Braswell include SPI serial flash host

controller which is used to hold BIOS and other platform specific data.

Since contents of the SPI serial flash is crucial for machine to function,

it is typically protected by different hardware protection mechanisms to

avoid accidental (or on purpose) overwrite of the content.

Not all manufacturers protect the SPI serial flash, mainly because it

allows upgrading the BIOS image directly from an OS.

The intel-spi driver makes it possible to read and write the SPI serial

flash, if certain protection bits are not set and locked. If it finds

any of them set, the whole MTD device is made read-only to prevent

partial overwrites. By default the driver exposes SPI serial flash

contents as read-only but it can be changed from kernel command line,

passing "intel-spi.writeable=1".

Please keep in mind that overwriting the BIOS image on SPI serial flash

might render the machine unbootable and requires special equipment like

Dediprog to revive. You have been warned!

Below are the steps how to upgrade MinnowBoard MAX BIOS directly from

Linux.

 1) Download and extract the latest Minnowboard MAX BIOS SPI image

    [1]. At the time writing this the latest image is v92.

 2) Install mtd-utils package [2]. We need this in order to erase the SPI

    serial flash. Distros like Debian and Fedora have this prepackaged with

    name "mtd-utils".

 3) Add "intel-spi.writeable=1" to the kernel command line and reboot

    the board (you can also reload the driver passing "writeable=1" as

    module parameter to modprobe).

 4) Once the board is up and running again, find the right MTD partition

    (it is named as "BIOS"):

    # cat /proc/mtd

    dev:    size   erasesize  name

    mtd0: 00800000 00001000 "BIOS"

    So here it will be /dev/mtd0 but it may vary.

 5) Make backup of the existing image first:

    # dd if=/dev/mtd0ro of=bios.bak

    16384+0 records in

    16384+0 records out

    8388608 bytes (8.4 MB) copied, 10.0269 s, 837 kB/s

 6) Verify the backup

    # sha1sum /dev/mtd0ro bios.bak

    fdbb011920572ca6c991377c4b418a0502668b73  /dev/mtd0ro

    fdbb011920572ca6c991377c4b418a0502668b73  bios.bak

    The SHA1 sums must match. Otherwise do not continue any further!

 7) Erase the SPI serial flash. After this step, do not reboot the

    board! Otherwise it will not start anymore.

    # flash_erase /dev/mtd0 0 0

    Erasing 4 Kibyte @ 7ff000 -- 100 % complete

 8) Once completed without errors you can write the new BIOS image:

    # dd if=MNW2MAX1.X64.0092.R01.1605221712.bin of=/dev/mtd0

 9) Verify that the new content of the SPI serial flash matches the new

    BIOS image:

    # sha1sum /dev/mtd0ro MNW2MAX1.X64.0092.R01.1605221712.bin

    9b4df9e4be2057fceec3a5529ec3d950836c87a2  /dev/mtd0ro

    9b4df9e4be2057fceec3a5529ec3d950836c87a2 MNW2MAX1.X64.0092.R01.1605221712.bin

    The SHA1 sums should match.

 10) Now you can reboot your board and observe the new BIOS starting up

     properly.

References

----------

[1] https://firmware.intel.com/sites/default/files/MinnowBoard.MAX_.X64.92.R01.zip

[2] http://www.linux-mtd.infradead.org/

 *	document number TBD : Wildcat Point-LP

 *	document number TBD : 9 Series

 *	document number TBD : Lewisburg

 *	document number TBD : Apollo Lake SoC

 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#define ACPIBASE_GCS_OFF	0x3410

#define ACPIBASE_GCS_END	0x3414

#define SPIBASE_BYT		0x54

#define SPIBASE_BYT_SZ		512

#define SPIBASE_BYT_EN		BIT(1)

#define SPIBASE_LPT		0x3800

#define SPIBASE_LPT_SZ		512

#define BCR			0xdc

#define BCR_WPD			BIT(0)

#define SPIBASE_APL_SZ		4096

#define GPIOBASE_ICH0		0x58

#define GPIOCTRL_ICH0		0x5C

#define GPIOBASE_ICH6		0x48

	},

};

static struct resource intel_spi_res[] = {

	{

		.flags = IORESOURCE_MEM,

	}

};

static struct mfd_cell lpc_ich_wdt_cell = {

	.name = "iTCO_wdt",

	.num_resources = ARRAY_SIZE(wdt_ich_res),

	.ignore_resource_conflicts = true,

};

static struct mfd_cell lpc_ich_spi_cell = {

	.name = "intel-spi",

	.num_resources = ARRAY_SIZE(intel_spi_res),

	.resources = intel_spi_res,

	.ignore_resource_conflicts = true,

};

/* chipset related info */

enum lpc_chipsets {

	LPC_ICH = 0,	/* ICH */

	LPC_BRASWELL,	/* Braswell SoC */

	LPC_LEWISBURG,	/* Lewisburg */

	LPC_9S,		/* 9 Series */

	LPC_APL,	/* Apollo Lake SoC */

};

static struct lpc_ich_info lpc_chipset_info[] = {

		.name = "Lynx Point",

		.iTCO_version = 2,

		.gpio_version = ICH_V5_GPIO,

		.spi_type = INTEL_SPI_LPT,

	},

	[LPC_LPT_LP] = {

		.name = "Lynx Point_LP",

		.iTCO_version = 2,

		.spi_type = INTEL_SPI_LPT,

	},

	[LPC_WBG] = {

		.name = "Wellsburg",

	[LPC_BAYTRAIL] = {

		.name = "Bay Trail SoC",

		.iTCO_version = 3,

		.spi_type = INTEL_SPI_BYT,

	},

	[LPC_COLETO] = {

		.name = "Coleto Creek",

	[LPC_WPT_LP] = {

		.name = "Wildcat Point_LP",

		.iTCO_version = 2,

		.spi_type = INTEL_SPI_LPT,

	},

	[LPC_BRASWELL] = {

		.name = "Braswell SoC",

		.iTCO_version = 3,

		.spi_type = INTEL_SPI_BYT,

	},

	[LPC_LEWISBURG] = {

		.name = "Lewisburg",

		.iTCO_version = 2,

		.gpio_version = ICH_V5_GPIO,

	},

	[LPC_APL] = {

		.name = "Apollo Lake SoC",

		.spi_type = INTEL_SPI_BXT,

	},

};

/*

	{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},

	{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},

	{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},

	{ PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},

	{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},

	{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},

	{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},

	return ret;

}

static int lpc_ich_init_spi(struct pci_dev *dev)

{

	struct lpc_ich_priv *priv = pci_get_drvdata(dev);

	struct resource *res = &intel_spi_res[0];

	struct intel_spi_boardinfo *info;

	u32 spi_base, rcba, bcr;

	info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);

	if (!info)

		return -ENOMEM;

	info->type = lpc_chipset_info[priv->chipset].spi_type;

	switch (info->type) {

	case INTEL_SPI_BYT:

		pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);

		if (spi_base & SPIBASE_BYT_EN) {

			res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);

			res->end = res->start + SPIBASE_BYT_SZ - 1;

		}

		break;

	case INTEL_SPI_LPT:

		pci_read_config_dword(dev, RCBABASE, &rcba);

		if (rcba & 1) {

			spi_base = round_down(rcba, SPIBASE_LPT_SZ);

			res->start = spi_base + SPIBASE_LPT;

			res->end = res->start + SPIBASE_LPT_SZ - 1;

			/*

			 * Try to make the flash chip writeable now by

			 * setting BCR_WPD. It it fails we tell the driver

			 * that it can only read the chip.

			 */

			pci_read_config_dword(dev, BCR, &bcr);

			if (!(bcr & BCR_WPD)) {

				bcr |= BCR_WPD;

				pci_write_config_dword(dev, BCR, bcr);

				pci_read_config_dword(dev, BCR, &bcr);

			}

			info->writeable = !!(bcr & BCR_WPD);

		}

		break;

	case INTEL_SPI_BXT: {

		unsigned int p2sb = PCI_DEVFN(13, 0);

		unsigned int spi = PCI_DEVFN(13, 2);

		struct pci_bus *bus = dev->bus;

		/*

		 * The P2SB is hidden by BIOS and we need to unhide it in

		 * order to read BAR of the SPI flash device. Once that is

		 * done we hide it again.

		 */

		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);

		pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,

					  &spi_base);

		if (spi_base != ~0) {

			res->start = spi_base & 0xfffffff0;

			res->end = res->start + SPIBASE_APL_SZ - 1;

			pci_bus_read_config_dword(bus, spi, BCR, &bcr);

			if (!(bcr & BCR_WPD)) {

				bcr |= BCR_WPD;

				pci_bus_write_config_dword(bus, spi, BCR, bcr);

				pci_bus_read_config_dword(bus, spi, BCR, &bcr);

			}

			info->writeable = !!(bcr & BCR_WPD);

		}

		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);

		break;

	}

	default:

		return -EINVAL;

	}

	if (!res->start)

		return -ENODEV;

	lpc_ich_spi_cell.platform_data = info;

	lpc_ich_spi_cell.pdata_size = sizeof(*info);

	return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,

			       &lpc_ich_spi_cell, 1, NULL, 0, NULL);

}

static int lpc_ich_probe(struct pci_dev *dev,

				const struct pci_device_id *id)

{

			cell_added = true;

	}

	if (lpc_chipset_info[priv->chipset].spi_type) {

		ret = lpc_ich_init_spi(dev);

		if (!ret)

			cell_added = true;

	}

	/*

	 * We only care if at least one or none of the cells registered

	 * successfully.