drm/nouveau/disp: port vblank handling to event interface (1d7c71a3) · Commits · e / devices / android_kernel_teracube_mt6765

drivers/gpu/drm/nouveau/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -143,6 +143,7 @@ nouveau-y += core/engine/copy/nvc0.o
	nouveau-y += core/engine/copy/nve0.o		nouveau-y += core/engine/copy/nve0.o
	nouveau-y += core/engine/crypt/nv84.o		nouveau-y += core/engine/crypt/nv84.o
	nouveau-y += core/engine/crypt/nv98.o		nouveau-y += core/engine/crypt/nv98.o
			nouveau-y += core/engine/disp/base.o
	nouveau-y += core/engine/disp/nv04.o		nouveau-y += core/engine/disp/nv04.o
	nouveau-y += core/engine/disp/nv50.o		nouveau-y += core/engine/disp/nv50.o
	nouveau-y += core/engine/disp/nv84.o		nouveau-y += core/engine/disp/nv84.o

drivers/gpu/drm/nouveau/core/engine/disp/base.c

0 → 100644

+52 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Copyright 2013 Red Hat Inc.
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice shall be included in
			* all copies or substantial portions of the Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
			* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
			* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
			* OTHER DEALINGS IN THE SOFTWARE.
			*
			* Authors: Ben Skeggs
			*/

			#include <engine/disp.h>

			void
			_nouveau_disp_dtor(struct nouveau_object *object)
			{
			struct nouveau_disp disp = (void )object;
			nouveau_event_destroy(&disp->vblank);
			nouveau_engine_destroy(&disp->base);
			}

			int
			nouveau_disp_create_(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, int heads,
			const char intname, const char extname,
			int length, void **pobject)
			{
			struct nouveau_disp *disp;
			int ret;

			ret = nouveau_engine_create_(parent, engine, oclass, true,
			intname, extname, length, pobject);
			disp = *pobject;
			if (ret)
			return ret;

			return nouveau_event_create(heads, &disp->vblank);
			}

drivers/gpu/drm/nouveau/core/engine/disp/nv04.c

+22 −9

Original line number	Original line	Diff line number	Diff line
	@@ -23,6 +23,8 @@
	*/		*/

	#include <engine/disp.h>		#include <engine/disp.h>

			#include <core/event.h>
	#include <core/class.h>		#include <core/class.h>

	struct nv04_disp_priv {		struct nv04_disp_priv {
	@@ -35,12 +37,20 @@ nv04_disp_sclass[] = {
	{},		{},
	};		};

			/*******************************************************************************
			* Display engine implementation
			******************************************************************************/

			static void
			nv04_disp_vblank_enable(struct nouveau_event *event, int head)
			{
			nv_wr32(event->priv, 0x600140 + (head * 0x2000) , 0x00000001);
			}

	static void		static void
	nv04_disp_intr_vblank(struct nv04_disp_priv *priv, int crtc)		nv04_disp_vblank_disable(struct nouveau_event *event, int head)
	{		{
	struct nouveau_disp *disp = &priv->base;		nv_wr32(event->priv, 0x600140 + (head * 0x2000) , 0x00000000);
	if (disp->vblank.notify)
	disp->vblank.notify(disp->vblank.data, crtc);
	}		}

	static void		static void
	@@ -51,12 +61,12 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
	u32 crtc1 = nv_rd32(priv, 0x602100);		u32 crtc1 = nv_rd32(priv, 0x602100);

	if (crtc0 & 0x00000001) {		if (crtc0 & 0x00000001) {
	nv04_disp_intr_vblank(priv, 0);		nouveau_event_trigger(priv->base.vblank, 0);
	nv_wr32(priv, 0x600100, 0x00000001);		nv_wr32(priv, 0x600100, 0x00000001);
	}		}

	if (crtc1 & 0x00000001) {		if (crtc1 & 0x00000001) {
	nv04_disp_intr_vblank(priv, 1);		nouveau_event_trigger(priv->base.vblank, 1);
	nv_wr32(priv, 0x602100, 0x00000001);		nv_wr32(priv, 0x602100, 0x00000001);
	}		}
	}		}
	@@ -69,7 +79,7 @@ nv04_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	struct nv04_disp_priv *priv;		struct nv04_disp_priv *priv;
	int ret;		int ret;

	ret = nouveau_disp_create(parent, engine, oclass, "DISPLAY",		ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY",
	"display", &priv);		"display", &priv);
	*pobject = nv_object(priv);		*pobject = nv_object(priv);
	if (ret)		if (ret)
	@@ -77,6 +87,9 @@ nv04_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,

	nv_engine(priv)->sclass = nv04_disp_sclass;		nv_engine(priv)->sclass = nv04_disp_sclass;
	nv_subdev(priv)->intr = nv04_disp_intr;		nv_subdev(priv)->intr = nv04_disp_intr;
			priv->base.vblank->priv = priv;
			priv->base.vblank->enable = nv04_disp_vblank_enable;
			priv->base.vblank->disable = nv04_disp_vblank_disable;
	return 0;		return 0;
	}		}

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+18 −52

Original line number	Original line	Diff line number	Diff line
	@@ -27,7 +27,6 @@
	#include <core/handle.h>		#include <core/handle.h>
	#include <core/class.h>		#include <core/class.h>

	#include <engine/software.h>
	#include <engine/disp.h>		#include <engine/disp.h>

	#include <subdev/bios.h>		#include <subdev/bios.h>
	@@ -37,7 +36,6 @@
	#include <subdev/bios/pll.h>		#include <subdev/bios/pll.h>
	#include <subdev/timer.h>		#include <subdev/timer.h>
	#include <subdev/fb.h>		#include <subdev/fb.h>
	#include <subdev/bar.h>
	#include <subdev/clock.h>		#include <subdev/clock.h>

	#include "nv50.h"		#include "nv50.h"
	@@ -543,6 +541,18 @@ nv50_disp_curs_ofuncs = {
	* Base display object		* Base display object
	******************************************************************************/		******************************************************************************/

			static void
			nv50_disp_base_vblank_enable(struct nouveau_event *event, int head)
			{
			nv_mask(event->priv, 0x61002c, (1 << head), (1 << head));
			}

			static void
			nv50_disp_base_vblank_disable(struct nouveau_event *event, int head)
			{
			nv_mask(event->priv, 0x61002c, (1 << head), (0 << head));
			}

	static int		static int
	nv50_disp_base_ctor(struct nouveau_object *parent,		nv50_disp_base_ctor(struct nouveau_object *parent,
	struct nouveau_object *engine,		struct nouveau_object *engine,
	@@ -559,6 +569,9 @@ nv50_disp_base_ctor(struct nouveau_object *parent,
	if (ret)		if (ret)
	return ret;		return ret;

			priv->base.vblank->priv = priv;
			priv->base.vblank->enable = nv50_disp_base_vblank_enable;
			priv->base.vblank->disable = nv50_disp_base_vblank_disable;
	return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht);		return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht);
	}		}

	@@ -756,50 +769,6 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv)
	}		}
	}		}

	static void
	nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
	{
	struct nouveau_bar *bar = nouveau_bar(priv);
	struct nouveau_disp *disp = &priv->base;
	struct nouveau_software_chan chan, temp;
	unsigned long flags;

	spin_lock_irqsave(&disp->vblank.lock, flags);
	list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
	if (chan->vblank.crtc != crtc)
	continue;

	if (nv_device(priv)->chipset >= 0xc0) {
	nv_wr32(priv, 0x001718, 0x80000000 \| chan->vblank.channel);
	bar->flush(bar);
	nv_wr32(priv, 0x06000c,
	upper_32_bits(chan->vblank.offset));
	nv_wr32(priv, 0x060010,
	lower_32_bits(chan->vblank.offset));
	nv_wr32(priv, 0x060014, chan->vblank.value);
	} else {
	nv_wr32(priv, 0x001704, chan->vblank.channel);
	nv_wr32(priv, 0x001710, 0x80000000 \| chan->vblank.ctxdma);
	bar->flush(bar);
	if (nv_device(priv)->chipset == 0x50) {
	nv_wr32(priv, 0x001570, chan->vblank.offset);
	nv_wr32(priv, 0x001574, chan->vblank.value);
	} else {
	nv_wr32(priv, 0x060010, chan->vblank.offset);
	nv_wr32(priv, 0x060014, chan->vblank.value);
	}
	}

	list_del(&chan->vblank.head);
	if (disp->vblank.put)
	disp->vblank.put(disp->vblank.data, crtc);
	}
	spin_unlock_irqrestore(&disp->vblank.lock, flags);

	if (disp->vblank.notify)
	disp->vblank.notify(disp->vblank.data, crtc);
	}

	static u16		static u16
	exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,		exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
	struct dcb_output dcb, u8 ver, u8 hdr, u8 cnt, u8 *len,		struct dcb_output dcb, u8 ver, u8 hdr, u8 cnt, u8 *len,
	@@ -1201,13 +1170,13 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
	}		}

	if (intr1 & 0x00000004) {		if (intr1 & 0x00000004) {
	nv50_disp_intr_vblank(priv, 0);		nouveau_event_trigger(priv->base.vblank, 0);
	nv_wr32(priv, 0x610024, 0x00000004);		nv_wr32(priv, 0x610024, 0x00000004);
	intr1 &= ~0x00000004;		intr1 &= ~0x00000004;
	}		}

	if (intr1 & 0x00000008) {		if (intr1 & 0x00000008) {
	nv50_disp_intr_vblank(priv, 1);		nouveau_event_trigger(priv->base.vblank, 1);
	nv_wr32(priv, 0x610024, 0x00000008);		nv_wr32(priv, 0x610024, 0x00000008);
	intr1 &= ~0x00000008;		intr1 &= ~0x00000008;
	}		}
	@@ -1226,7 +1195,7 @@ nv50_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	struct nv50_disp_priv *priv;		struct nv50_disp_priv *priv;
	int ret;		int ret;

	ret = nouveau_disp_create(parent, engine, oclass, "PDISP",		ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
	"display", &priv);		"display", &priv);
	*pobject = nv_object(priv);		*pobject = nv_object(priv);
	if (ret)		if (ret)
	@@ -1242,9 +1211,6 @@ nv50_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	priv->dac.power = nv50_dac_power;		priv->dac.power = nv50_dac_power;
	priv->dac.sense = nv50_dac_sense;		priv->dac.sense = nv50_dac_sense;
	priv->sor.power = nv50_sor_power;		priv->sor.power = nv50_sor_power;

	INIT_LIST_HEAD(&priv->base.vblank.list);
	spin_lock_init(&priv->base.vblank.lock);
	return 0;		return 0;
	}		}

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -3,7 +3,9 @@

	#include <core/parent.h>		#include <core/parent.h>
	#include <core/namedb.h>		#include <core/namedb.h>
			#include <core/engctx.h>
	#include <core/ramht.h>		#include <core/ramht.h>
			#include <core/event.h>

	#include <engine/dmaobj.h>		#include <engine/dmaobj.h>
	#include <engine/disp.h>		#include <engine/disp.h>