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Commit 04c4fab4 authored by vend_yanshoushuai001's avatar vend_yanshoushuai001 Committed by Cui Li
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[ALPS05460562] lcm driver:dsi timing refine 



[Detail] modify the pll clock

[Solution] modify the pll clock with data rate

MTK-Commit-Id: 6de0caa68f28f2e4a5244a78a8f64b78b2fcfa3f

Change-Id: I0ca132f9713e8d771621a690d274d1630724d434
CR-Id: ALPS05460562
Feature: [Module]Display Driver
Signed-off-by: default avatarvend_yanshoushuai001 <vend_yanshoushuai001@mediatek.com>
parent c7ffd9e8
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