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Commit f3368128 authored by Christian König's avatar Christian König Committed by Alex Deucher
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drm/amdgpu: move validation of the VM size into the VM code



This moves validation of the VM size parameter into amdgpu_vm_adjust_size().

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 341b759e
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+1 −15
Original line number Diff line number Diff line
@@ -1187,23 +1187,9 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
	if (amdgpu_vm_size < 1) {
		dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
			 amdgpu_vm_size);
		goto def_value;
	}

	/*
	 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
	 */
	if (amdgpu_vm_size > 1024) {
		dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
			 amdgpu_vm_size);
		goto def_value;
	}

	return;

def_value:
		amdgpu_vm_size = -1;
	}
}

/**
 * amdgpu_check_arguments - validate module params
+11 −2
Original line number Diff line number Diff line
@@ -2580,13 +2580,22 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
 * @vm_size: the default vm size if it's set auto
 */
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
			   uint32_t fragment_size_default, unsigned max_level)
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits)
{
	uint64_t tmp;

	/* adjust vm size first */
	if (amdgpu_vm_size != -1)
	if (amdgpu_vm_size != -1) {
		unsigned max_size = 1 << (max_bits - 30);

		vm_size = amdgpu_vm_size;
		if (vm_size > max_size) {
			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
				 amdgpu_vm_size, max_size);
			vm_size = max_size;
		}
	}

	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;

+2 −1
Original line number Diff line number Diff line
@@ -325,7 +325,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
			   uint32_t fragment_size_default, unsigned max_level);
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job);
+1 −1
Original line number Diff line number Diff line
@@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle)
	if (r)
		return r;

	amdgpu_vm_adjust_size(adev, 64, 9, 1);
	amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);

	adev->mc.mc_mask = 0xffffffffffULL;

+1 −1
Original line number Diff line number Diff line
@@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle)
	 * Currently set to 4GB ((1 << 20) 4k pages).
	 * Max GPUVM size for cayman and SI is 40 bits.
	 */
	amdgpu_vm_adjust_size(adev, 64, 9, 1);
	amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);

	/* Set the internal MC address mask
	 * This is the max address of the GPU's
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