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Commit f061de42 authored by Hariprasad Shenai's avatar Hariprasad Shenai Committed by David S. Miller
Browse files

cxgb4/cxgb4vf/csiostor: Cleanup SGE and PCI related register defines 



This patch cleansup remaining SGE related macros/register defines and all PCI
related ones that are defined in t4_regs.h and the affected files.

Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f612b815

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+34 −34
Original line number Diff line number Diff line
@@ -1590,9 +1590,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats, 
	collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);

	data += sizeof(struct queue_port_stats) / sizeof(u64);

	if (!is_t4(adapter->params.chip)) {

		t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));

		val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);

		val2 = t4_read_reg(adapter, SGE_STAT_MATCH);

		t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7));

		val1 = t4_read_reg(adapter, SGE_STAT_TOTAL_A);

		val2 = t4_read_reg(adapter, SGE_STAT_MATCH_A);

		*data = val1 - val2;

		data++;

		*data = val2;
@@ -3601,14 +3601,14 @@ unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 
	struct adapter *adap = netdev2adap(dev);

	u32 v1, v2, lp_count, hp_count;



	v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);

	v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);

	v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);

	v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);

	if (is_t4(adap->params.chip)) {

		lp_count = G_LP_COUNT(v1);

		hp_count = G_HP_COUNT(v1);

		lp_count = LP_COUNT_G(v1);

		hp_count = HP_COUNT_G(v1);

	} else {

		lp_count = G_LP_COUNT_T5(v1);

		hp_count = G_HP_COUNT_T5(v2);

		lp_count = LP_COUNT_T5_G(v1);

		hp_count = HP_COUNT_T5_G(v2);

	}

	return lpfifo ? lp_count : hp_count;

}
@@ -3667,14 +3667,14 @@ int cxgb4_flush_eq_cache(struct net_device *dev) 
	int ret;



	ret = t4_fwaddrspace_write(adap, adap->mbox,

				   0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);

				   0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);

	return ret;

}

EXPORT_SYMBOL(cxgb4_flush_eq_cache);



static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)

{

	u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;

	u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;

	__be64 indices;

	int ret;
@@ -3728,7 +3728,7 @@ void cxgb4_disable_db_coalescing(struct net_device *dev) 
	struct adapter *adap;



	adap = netdev2adap(dev);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F,

	t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,

			 NOCOALESCE_F);

}

EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
@@ -3738,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev) 
	struct adapter *adap;



	adap = netdev2adap(dev);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 0);

	t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);

}

EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
@@ -3877,14 +3877,14 @@ static void drain_db_fifo(struct adapter *adap, int usecs) 
	u32 v1, v2, lp_count, hp_count;



	do {

		v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);

		v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);

		v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);

		v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);

		if (is_t4(adap->params.chip)) {

			lp_count = G_LP_COUNT(v1);

			hp_count = G_HP_COUNT(v1);

			lp_count = LP_COUNT_G(v1);

			hp_count = HP_COUNT_G(v1);

		} else {

			lp_count = G_LP_COUNT_T5(v1);

			hp_count = G_HP_COUNT_T5(v2);

			lp_count = LP_COUNT_T5_G(v1);

			hp_count = HP_COUNT_T5_G(v2);

		}



		if (lp_count == 0 && hp_count == 0)
@@ -4044,7 +4044,7 @@ static void process_db_drop(struct work_struct *work) 
		t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);

	}



	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);

	t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);

}



void t4_db_full(struct adapter *adap)
@@ -4871,16 +4871,16 @@ static void setup_memwin(struct adapter *adap) 
		mem_win2_base = MEMWIN2_BASE_T5;

		mem_win2_aperture = MEMWIN2_APERTURE_T5;

	}

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),

		     mem_win0_base | BIR(0) |

		     WINDOW(ilog2(MEMWIN0_APERTURE) - 10));

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),

		     mem_win1_base | BIR(0) |

		     WINDOW(ilog2(MEMWIN1_APERTURE) - 10));

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),

		     mem_win2_base | BIR(0) |

		     WINDOW(ilog2(mem_win2_aperture) - 10));

	t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),

		     mem_win0_base | BIR_V(0) |

		     WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),

		     mem_win1_base | BIR_V(0) |

		     WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));

	t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),

		     mem_win2_base | BIR_V(0) |

		     WINDOW_V(ilog2(mem_win2_aperture) - 10));

	t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));

}



static void setup_memwin_rdma(struct adapter *adap)
@@ -4894,13 +4894,13 @@ static void setup_memwin_rdma(struct adapter *adap) 
		start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);

		sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;

		t4_write_reg(adap,

			     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),

			     start | BIR(1) | WINDOW(ilog2(sz_kb)));

			     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),

			     start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));

		t4_write_reg(adap,

			     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),

			     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),

			     adap->vres.ocq.start);

		t4_read_reg(adap,

			    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));

			    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));

	}

}

drivers/net/ethernet/chelsio/cxgb4/sge.c

+39 −39
Original line number Diff line number Diff line
@@ -2098,7 +2098,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie) 
{

	struct adapter *adap = cookie;



	t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);

	t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);

	if (t4_slow_intr_handler(adap) | process_intrq(adap))

		return IRQ_HANDLED;

	return IRQ_NONE;             /* probably shared interrupt */
@@ -2145,9 +2145,9 @@ static void sge_rx_timer_cb(unsigned long data) 
			}

		}



	t4_write_reg(adap, SGE_DEBUG_INDEX, 13);

	idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);

	idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);

	t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);

	idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);

	idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);



	for (i = 0; i < 2; i++) {

		u32 debug0, debug11;
@@ -2191,12 +2191,12 @@ static void sge_rx_timer_cb(unsigned long data) 
		/* Read and save the SGE IDMA State and Queue ID information.

		 * We do this every time in case it changes across time ...

		 */

		t4_write_reg(adap, SGE_DEBUG_INDEX, 0);

		debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);

		t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);

		debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);

		s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;



		t4_write_reg(adap, SGE_DEBUG_INDEX, 11);

		debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);

		t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);

		debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);

		s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;



		CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
@@ -2826,21 +2826,21 @@ static int t4_sge_init_soft(struct adapter *adap) 
	 * Retrieve our RX interrupt holdoff timer values and counter

	 * threshold values from the SGE parameters.

	 */

	timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1);

	timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3);

	timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5);

	timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);

	timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);

	timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);

	s->timer_val[0] = core_ticks_to_us(adap,

		TIMERVALUE0_GET(timer_value_0_and_1));

		TIMERVALUE0_G(timer_value_0_and_1));

	s->timer_val[1] = core_ticks_to_us(adap,

		TIMERVALUE1_GET(timer_value_0_and_1));

		TIMERVALUE1_G(timer_value_0_and_1));

	s->timer_val[2] = core_ticks_to_us(adap,

		TIMERVALUE2_GET(timer_value_2_and_3));

		TIMERVALUE2_G(timer_value_2_and_3));

	s->timer_val[3] = core_ticks_to_us(adap,

		TIMERVALUE3_GET(timer_value_2_and_3));

		TIMERVALUE3_G(timer_value_2_and_3));

	s->timer_val[4] = core_ticks_to_us(adap,

		TIMERVALUE4_GET(timer_value_4_and_5));

		TIMERVALUE4_G(timer_value_4_and_5));

	s->timer_val[5] = core_ticks_to_us(adap,

		TIMERVALUE5_GET(timer_value_4_and_5));

		TIMERVALUE5_G(timer_value_4_and_5));



	ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);

	s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
@@ -2866,21 +2866,21 @@ static int t4_sge_init_hard(struct adapter *adap) 
	 * and generate an interrupt when this occurs so we can recover.

	 */

	if (is_t4(adap->params.chip)) {

		t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,

				 V_HP_INT_THRESH(M_HP_INT_THRESH) |

				 V_LP_INT_THRESH(M_LP_INT_THRESH),

				 V_HP_INT_THRESH(dbfifo_int_thresh) |

				 V_LP_INT_THRESH(dbfifo_int_thresh));

		t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,

				 HP_INT_THRESH_V(HP_INT_THRESH_M) |

				 LP_INT_THRESH_V(LP_INT_THRESH_M),

				 HP_INT_THRESH_V(dbfifo_int_thresh) |

				 LP_INT_THRESH_V(dbfifo_int_thresh));

	} else {

		t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,

				 V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),

				 V_LP_INT_THRESH_T5(dbfifo_int_thresh));

		t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,

				 V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),

				 V_HP_INT_THRESH_T5(dbfifo_int_thresh));

		t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,

				 LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),

				 LP_INT_THRESH_T5_V(dbfifo_int_thresh));

		t4_set_reg_field(adap, SGE_DBFIFO_STATUS2_A,

				 HP_INT_THRESH_T5_V(HP_INT_THRESH_T5_M),

				 HP_INT_THRESH_T5_V(dbfifo_int_thresh));

	}

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,

			F_ENABLE_DROP);

	t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,

			 ENABLE_DROP_F);



	/*

	 * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
@@ -2905,15 +2905,15 @@ static int t4_sge_init_hard(struct adapter *adap) 
		     THRESHOLD_1_V(s->counter_val[1]) |

		     THRESHOLD_2_V(s->counter_val[2]) |

		     THRESHOLD_3_V(s->counter_val[3]));

	t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,

		     TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |

		     TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));

	t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,

		     TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) |

		     TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3])));

	t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,

		     TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) |

		     TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5])));

	t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1_A,

		     TIMERVALUE0_V(us_to_core_ticks(adap, s->timer_val[0])) |

		     TIMERVALUE1_V(us_to_core_ticks(adap, s->timer_val[1])));

	t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3_A,

		     TIMERVALUE2_V(us_to_core_ticks(adap, s->timer_val[2])) |

		     TIMERVALUE3_V(us_to_core_ticks(adap, s->timer_val[3])));

	t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5_A,

		     TIMERVALUE4_V(us_to_core_ticks(adap, s->timer_val[4])) |

		     TIMERVALUE5_V(us_to_core_ticks(adap, s->timer_val[5])));



	return 0;

}

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+113 −111
Original line number Diff line number Diff line
@@ -150,20 +150,20 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 
 */

void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)

{

	u32 req = ENABLE | FUNCTION(adap->fn) | reg;

	u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);



	if (is_t4(adap->params.chip))

		req |= F_LOCALCFG;

		req |= LOCALCFG_F;



	t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);

	*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);

	t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);

	*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);



	/* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a

	 * Configuration Space read.  (None of the other fields matter when

	 * ENABLE is 0 so a simple register write is easier than a

	 * read-modify-write via t4_set_reg_field().)

	 */

	t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);

	t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);

}



/*
@@ -188,8 +188,8 @@ static void t4_report_fw_error(struct adapter *adap) 
	};

	u32 pcie_fw;



	pcie_fw = t4_read_reg(adap, MA_PCIE_FW);

	if (pcie_fw & PCIE_FW_ERR)

	pcie_fw = t4_read_reg(adap, PCIE_FW_A);

	if (pcie_fw & PCIE_FW_ERR_F)

		dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",

			reason[PCIE_FW_EVAL_G(pcie_fw)]);

}
@@ -506,13 +506,13 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, 
	 * the address is relative to BAR0.

	 */

	mem_reg = t4_read_reg(adap,

			      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,

			      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,

						  win));

	mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);

	mem_base = GET_PCIEOFST(mem_reg) << 10;

	mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);

	mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;

	if (is_t4(adap->params.chip))

		mem_base -= adap->t4_bar0;

	win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);

	win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);



	/* Calculate our initial PCI-E Memory Window Position and Offset into

	 * that Window.
@@ -525,10 +525,10 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, 
	 * attempt to use the new value.)

	 */

	t4_write_reg(adap,

		     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),

		     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),

		     pos | win_pf);

	t4_read_reg(adap,

		    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));

		    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));



	/* Transfer data to/from the adapter as long as there's an integral

	 * number of 32-bit transfers to complete.
@@ -553,10 +553,10 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, 
			pos += mem_aperture;

			offset = 0;

			t4_write_reg(adap,

				     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,

				PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,

						    win), pos | win_pf);

			t4_read_reg(adap,

				    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,

				PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,

						    win));

		}

	}
@@ -1366,95 +1366,97 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 
static void pcie_intr_handler(struct adapter *adapter)

{

	static const struct intr_info sysbus_intr_info[] = {

		{ RNPP, "RXNP array parity error", -1, 1 },

		{ RPCP, "RXPC array parity error", -1, 1 },

		{ RCIP, "RXCIF array parity error", -1, 1 },

		{ RCCP, "Rx completions control array parity error", -1, 1 },

		{ RFTP, "RXFT array parity error", -1, 1 },

		{ RNPP_F, "RXNP array parity error", -1, 1 },

		{ RPCP_F, "RXPC array parity error", -1, 1 },

		{ RCIP_F, "RXCIF array parity error", -1, 1 },

		{ RCCP_F, "Rx completions control array parity error", -1, 1 },

		{ RFTP_F, "RXFT array parity error", -1, 1 },

		{ 0 }

	};

	static const struct intr_info pcie_port_intr_info[] = {

		{ TPCP, "TXPC array parity error", -1, 1 },

		{ TNPP, "TXNP array parity error", -1, 1 },

		{ TFTP, "TXFT array parity error", -1, 1 },

		{ TCAP, "TXCA array parity error", -1, 1 },

		{ TCIP, "TXCIF array parity error", -1, 1 },

		{ RCAP, "RXCA array parity error", -1, 1 },

		{ OTDD, "outbound request TLP discarded", -1, 1 },

		{ RDPE, "Rx data parity error", -1, 1 },

		{ TDUE, "Tx uncorrectable data error", -1, 1 },

		{ TPCP_F, "TXPC array parity error", -1, 1 },

		{ TNPP_F, "TXNP array parity error", -1, 1 },

		{ TFTP_F, "TXFT array parity error", -1, 1 },

		{ TCAP_F, "TXCA array parity error", -1, 1 },

		{ TCIP_F, "TXCIF array parity error", -1, 1 },

		{ RCAP_F, "RXCA array parity error", -1, 1 },

		{ OTDD_F, "outbound request TLP discarded", -1, 1 },

		{ RDPE_F, "Rx data parity error", -1, 1 },

		{ TDUE_F, "Tx uncorrectable data error", -1, 1 },

		{ 0 }

	};

	static const struct intr_info pcie_intr_info[] = {

		{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },

		{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },

		{ MSIDATAPERR, "MSI data parity error", -1, 1 },

		{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },

		{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },

		{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },

		{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },

		{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },

		{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },

		{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },

		{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },

		{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },

		{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },

		{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },

		{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },

		{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },

		{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },

		{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },

		{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },

		{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },

		{ FIDPERR, "PCI FID parity error", -1, 1 },

		{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },

		{ MATAGPERR, "PCI MA tag parity error", -1, 1 },

		{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },

		{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },

		{ RXWRPERR, "PCI Rx write parity error", -1, 1 },

		{ RPLPERR, "PCI replay buffer parity error", -1, 1 },

		{ PCIESINT, "PCI core secondary fault", -1, 1 },

		{ PCIEPINT, "PCI core primary fault", -1, 1 },

		{ UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },

		{ MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },

		{ MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },

		{ MSIDATAPERR_F, "MSI data parity error", -1, 1 },

		{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },

		{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },

		{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },

		{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },

		{ PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },

		{ PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },

		{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },

		{ CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },

		{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },

		{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },

		{ DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },

		{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },

		{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },

		{ HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },

		{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },

		{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },

		{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },

		{ FIDPERR_F, "PCI FID parity error", -1, 1 },

		{ INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },

		{ MATAGPERR_F, "PCI MA tag parity error", -1, 1 },

		{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },

		{ RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },

		{ RXWRPERR_F, "PCI Rx write parity error", -1, 1 },

		{ RPLPERR_F, "PCI replay buffer parity error", -1, 1 },

		{ PCIESINT_F, "PCI core secondary fault", -1, 1 },

		{ PCIEPINT_F, "PCI core primary fault", -1, 1 },

		{ UNXSPLCPLERR_F, "PCI unexpected split completion error",

		  -1, 0 },

		{ 0 }

	};



	static struct intr_info t5_pcie_intr_info[] = {

		{ MSTGRPPERR, "Master Response Read Queue parity error",

		{ MSTGRPPERR_F, "Master Response Read Queue parity error",

		  -1, 1 },

		{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },

		{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },

		{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },

		{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },

		{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },

		{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },

		{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",

		{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },

		{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },

		{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },

		{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },

		{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },

		{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },

		{ PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",

		  -1, 1 },

		{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",

		{ PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",

		  -1, 1 },

		{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },

		{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },

		{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },

		{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },

		{ DREQWRPERR, "PCI DMA channel write request parity error",

		{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },

		{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },

		{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },

		{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },

		{ DREQWRPERR_F, "PCI DMA channel write request parity error",

		  -1, 1 },

		{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },

		{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },

		{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },

		{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },

		{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },

		{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },

		{ FIDPERR, "PCI FID parity error", -1, 1 },

		{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },

		{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },

		{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },

		{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",

		{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },

		{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },

		{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },

		{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },

		{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },

		{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },

		{ FIDPERR_F, "PCI FID parity error", -1, 1 },

		{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },

		{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },

		{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },

		{ IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",

		  -1, 1 },

		{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },

		{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },

		{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },

		{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },

		{ READRSPERR, "Outbound read error", -1, 0 },

		{ IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",

		  -1, 1 },

		{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },

		{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },

		{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },

		{ READRSPERR_F, "Outbound read error", -1, 0 },

		{ 0 }

	};
@@ -1462,15 +1464,15 @@ static void pcie_intr_handler(struct adapter *adapter) 


	if (is_t4(adapter->params.chip))

		fat = t4_handle_intr_status(adapter,

					    PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,

				PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,

				sysbus_intr_info) +

			t4_handle_intr_status(adapter,

					      PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,

					PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,

					pcie_port_intr_info) +

			t4_handle_intr_status(adapter, PCIE_INT_CAUSE,

			t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,

					      pcie_intr_info);

	else

		fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,

		fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,

					    t5_pcie_intr_info);



	if (fat)
@@ -1590,7 +1592,7 @@ static void cim_intr_handler(struct adapter *adapter) 


	int fat;



	if (t4_read_reg(adapter, MA_PCIE_FW) & PCIE_FW_ERR)

	if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)

		t4_report_fw_error(adapter);



	fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
@@ -2750,9 +2752,9 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state) 
		"IDMA_FL_SEND_COMPLETION_TO_IMSG",

	};

	static const u32 sge_regs[] = {

		SGE_DEBUG_DATA_LOW_INDEX_2,

		SGE_DEBUG_DATA_LOW_INDEX_3,

		SGE_DEBUG_DATA_HIGH_INDEX_10,

		SGE_DEBUG_DATA_LOW_INDEX_2_A,

		SGE_DEBUG_DATA_LOW_INDEX_3_A,

		SGE_DEBUG_DATA_HIGH_INDEX_10_A,

	};

	const char **sge_idma_decode;

	int sge_idma_decode_nstates;
@@ -2819,7 +2821,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
	if (ret < 0) {

		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)

			goto retry;

		if (t4_read_reg(adap, MA_PCIE_FW) & PCIE_FW_ERR)

		if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)

			t4_report_fw_error(adap);

		return ret;

	}
@@ -2869,8 +2871,8 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
			 * timeout ... and then retry if we haven't exhausted

			 * our retries ...

			 */

			pcie_fw = t4_read_reg(adap, MA_PCIE_FW);

			if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {

			pcie_fw = t4_read_reg(adap, PCIE_FW_A);

			if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {

				if (waiting <= 0) {

					if (retries-- > 0)

						goto retry;
@@ -2885,9 +2887,9 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
			 * report errors preferentially.

			 */

			if (state) {

				if (pcie_fw & PCIE_FW_ERR)

				if (pcie_fw & PCIE_FW_ERR_F)

					*state = DEV_STATE_ERR;

				else if (pcie_fw & PCIE_FW_INIT)

				else if (pcie_fw & PCIE_FW_INIT_F)

					*state = DEV_STATE_INIT;

			}
@@ -2897,7 +2899,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
			 * for our caller.

			 */

			if (master_mbox == PCIE_FW_MASTER_M &&

			    (pcie_fw & PCIE_FW_MASTER_VLD))

			    (pcie_fw & PCIE_FW_MASTER_VLD_F))

				master_mbox = PCIE_FW_MASTER_G(pcie_fw);

			break;

		}
@@ -3006,7 +3008,7 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 
	 */

	if (ret == 0 || force) {

		t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);

		t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F,

		t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,

				 PCIE_FW_HALT_F);

	}
@@ -3046,7 +3048,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 
		 * doing it automatically, we need to clear the PCIE_FW.HALT

		 * bit.

		 */

		t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 0);

		t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);



		/*

		 * If we've been given a valid mailbox, first try to get the
@@ -3070,7 +3072,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 


		t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);

		for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {

			if (!(t4_read_reg(adap, PCIE_FW) & PCIE_FW_HALT_F))

			if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))

				return 0;

			msleep(100);

			ms += 100;
@@ -4146,7 +4148,7 @@ int t4_init_sge_params(struct adapter *adapter) 
		(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);

	qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);

	sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);

	qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF);

	qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);

	sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);



	return 0;

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+416 −189

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/chelsio/cxgb4/t4_values.h

+4 −0
Original line number Diff line number Diff line
@@ -78,4 +78,8 @@ 
#define SGE_UDB_GTS		20

#define SGE_UDB_WCDOORBELL	64



/* PCI-E definitions */

#define WINDOW_SHIFT_X		10

#define PCIEOFST_SHIFT_X	10



#endif /* __T4_VALUES_H__ */