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Commit f612b815 authored by Hariprasad Shenai's avatar Hariprasad Shenai Committed by David S. Miller
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RDMA/cxgb4/cxgb4vf/csiostor: Cleanup SGE register defines 



This patch cleanups all SGE related macros/register defines that are
defined in t4_regs.h and the affected files.

Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5f07b3c5

drivers/infiniband/hw/cxgb4/t4.h

+13 −13
Original line number Diff line number Diff line
@@ -465,14 +465,14 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, 
		} else {

			PDBG("%s: DB wq->sq.pidx = %d\n",

			     __func__, wq->sq.pidx);

			writel(PIDX_T5(inc), wq->sq.udb);

			writel(PIDX_T5_V(inc), wq->sq.udb);

		}



		/* Flush user doorbell area writes. */

		wmb();

		return;

	}

	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);

	writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);

}



static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
@@ -489,14 +489,14 @@ static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, 
		} else {

			PDBG("%s: DB wq->rq.pidx = %d\n",

			     __func__, wq->rq.pidx);

			writel(PIDX_T5(inc), wq->rq.udb);

			writel(PIDX_T5_V(inc), wq->rq.udb);

		}



		/* Flush user doorbell area writes. */

		wmb();

		return;

	}

	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);

	writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);

}



static inline int t4_wq_in_error(struct t4_wq *wq)
@@ -561,14 +561,14 @@ static inline int t4_arm_cq(struct t4_cq *cq, int se) 
	u32 val;



	set_bit(CQ_ARMED, &cq->flags);

	while (cq->cidx_inc > CIDXINC_MASK) {

		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |

		      INGRESSQID(cq->cqid);

	while (cq->cidx_inc > CIDXINC_M) {

		val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7) |

		      INGRESSQID_V(cq->cqid);

		writel(val, cq->gts);

		cq->cidx_inc -= CIDXINC_MASK;

		cq->cidx_inc -= CIDXINC_M;

	}

	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |

	      INGRESSQID(cq->cqid);

	val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6) |

	      INGRESSQID_V(cq->cqid);

	writel(val, cq->gts);

	cq->cidx_inc = 0;

	return 0;
@@ -597,11 +597,11 @@ static inline void t4_swcq_consume(struct t4_cq *cq) 
static inline void t4_hwcq_consume(struct t4_cq *cq)

{

	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;

	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {

	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {

		u32 val;



		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |

		      INGRESSQID(cq->cqid);

		val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7) |

		      INGRESSQID_V(cq->cqid);

		writel(val, cq->gts);

		cq->cidx_inc = 0;

	}

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+45 −31
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ 


#include "cxgb4.h"

#include "t4_regs.h"

#include "t4_values.h"

#include "t4_msg.h"

#include "t4fw_api.h"

#include "cxgb4_dcb.h"
@@ -1050,9 +1051,9 @@ static void enable_rx(struct adapter *adap) 
		if (q->handler)

			napi_enable(&q->napi);

		/* 0-increment GTS to start the timer and enable interrupts */

		t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),

			     SEINTARM(q->intr_params) |

			     INGRESSQID(q->cntxt_id));

		t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),

			     SEINTARM_V(q->intr_params) |

			     INGRESSQID_V(q->cntxt_id));

	}

}
@@ -3702,14 +3703,20 @@ int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 


	if (pidx != hw_pidx) {

		u16 delta;

		u32 val;



		if (pidx >= hw_pidx)

			delta = pidx - hw_pidx;

		else

			delta = size - hw_pidx + pidx;



		if (is_t4(adap->params.chip))

			val = PIDX_V(delta);

		else

			val = PIDX_T5_V(delta);

		wmb();

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),

			     QID(qid) | PIDX(delta));

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),

			     QID_V(qid) | val);

	}

out:

	return ret;
@@ -3721,8 +3728,8 @@ void cxgb4_disable_db_coalescing(struct net_device *dev) 
	struct adapter *adap;



	adap = netdev2adap(dev);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,

			 F_NOCOALESCE);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F,

			 NOCOALESCE_F);

}

EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
@@ -3731,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev) 
	struct adapter *adap;



	adap = netdev2adap(dev);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);

	t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 0);

}

EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
@@ -3809,8 +3816,8 @@ u64 cxgb4_read_sge_timestamp(struct net_device *dev) 
	struct adapter *adap;



	adap = netdev2adap(dev);

	lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);

	hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));

	lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);

	hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));



	return ((u64)hi << 32) | (u64)lo;

}
@@ -3904,8 +3911,8 @@ static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 
		 * are committed before we tell HW about them.

		 */

		wmb();

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),

			     QID(q->cntxt_id) | PIDX(q->db_pidx_inc));

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),

			     QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));

		q->db_pidx_inc = 0;

	}

	q->db_disabled = 0;
@@ -3952,9 +3959,9 @@ static void process_db_full(struct work_struct *work) 
	drain_db_fifo(adap, dbfifo_drain_delay);

	enable_dbs(adap);

	notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);

	t4_set_reg_field(adap, SGE_INT_ENABLE3,

			 DBFIFO_HP_INT | DBFIFO_LP_INT,

			 DBFIFO_HP_INT | DBFIFO_LP_INT);

	t4_set_reg_field(adap, SGE_INT_ENABLE3_A,

			 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,

			 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);

}



static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
@@ -3968,14 +3975,20 @@ static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 
		goto out;

	if (q->db_pidx != hw_pidx) {

		u16 delta;

		u32 val;



		if (q->db_pidx >= hw_pidx)

			delta = q->db_pidx - hw_pidx;

		else

			delta = q->size - hw_pidx + q->db_pidx;



		if (is_t4(adap->params.chip))

			val = PIDX_V(delta);

		else

			val = PIDX_T5_V(delta);

		wmb();

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),

			     QID(q->cntxt_id) | PIDX(delta));

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),

			     QID_V(q->cntxt_id) | val);

	}

out:

	q->db_disabled = 0;
@@ -4024,7 +4037,7 @@ static void process_db_drop(struct work_struct *work) 
			dev_err(adap->pdev_dev, "doorbell drop recovery: "

				"qid=%d, pidx_inc=%d\n", qid, pidx_inc);

		else

			writel(PIDX_T5(pidx_inc) | QID(bar2_qid),

			writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),

			       adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);



		/* Re-enable BAR2 WC */
@@ -4039,8 +4052,8 @@ void t4_db_full(struct adapter *adap) 
	if (is_t4(adap->params.chip)) {

		disable_dbs(adap);

		notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);

		t4_set_reg_field(adap, SGE_INT_ENABLE3,

				 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);

		t4_set_reg_field(adap, SGE_INT_ENABLE3_A,

				 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);

		queue_work(adap->workq, &adap->db_full_task);

	}

}
@@ -4089,8 +4102,8 @@ static void uld_attach(struct adapter *adap, unsigned int uld) 
	/* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */

	for (i = 0; i < NCHAN; i++)

		lli.tx_modq[i] = i;

	lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);

	lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);

	lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);

	lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);

	lli.fw_vers = adap->params.fw_vers;

	lli.dbfifo_int_thresh = dbfifo_int_thresh;

	lli.sge_ingpadboundary = adap->sge.fl_align;
@@ -4783,7 +4796,7 @@ static const struct net_device_ops cxgb4_netdev_ops = { 


void t4_fatal_err(struct adapter *adap)

{

	t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);

	t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);

	t4_intr_disable(adap);

	dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");

}
@@ -5013,9 +5026,9 @@ static int adap_init0_tweaks(struct adapter *adapter) 
			rx_dma_offset);

		rx_dma_offset = 2;

	}

	t4_set_reg_field(adapter, SGE_CONTROL,

			 PKTSHIFT_MASK,

			 PKTSHIFT(rx_dma_offset));

	t4_set_reg_field(adapter, SGE_CONTROL_A,

			 PKTSHIFT_V(PKTSHIFT_M),

			 PKTSHIFT_V(rx_dma_offset));



	/*

	 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
@@ -5332,8 +5345,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset) 
	s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;

	s->counter_val[0] = 1;

	for (i = 1; i < SGE_NCOUNTERS; i++)

		s->counter_val[i] = min(intr_cnt[i - 1],

					THRESHOLD_0_GET(THRESHOLD_0_MASK));

		s->counter_val[i] = min(intr_cnt[i - 1], THRESHOLD_0_M);

	t4_sge_init(adapter);



#ifdef CONFIG_PCI_IOV
@@ -6467,9 +6479,11 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 




	if (!is_t4(adapter->params.chip)) {

		s_qpp = QUEUESPERPAGEPF1 * adapter->fn;

		qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,

		      SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);

		s_qpp = (QUEUESPERPAGEPF0_S +

			(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *

			adapter->fn);

		qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,

		      SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);

		num_seg = PAGE_SIZE / SEGMENT_SIZE;



		/* Each segment size is 128B. Write coalescing is enabled only

drivers/net/ethernet/chelsio/cxgb4/sge.c

+49 −47
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#include <net/tcp.h>

#include "cxgb4.h"

#include "t4_regs.h"

#include "t4_values.h"

#include "t4_msg.h"

#include "t4fw_api.h"
@@ -521,10 +522,12 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 
{

	u32 val;

	if (q->pend_cred >= 8) {

		val = PIDX(q->pend_cred / 8);

		if (!is_t4(adap->params.chip))

			val |= DBTYPE(1);

		val |= DBPRIO(1);

		if (is_t4(adap->params.chip))

			val = PIDX_V(q->pend_cred / 8);

		else

			val = PIDX_T5_V(q->pend_cred / 8) |

				DBTYPE_F;

		val |= DBPRIO_F;

		wmb();



		/* If we don't have access to the new User Doorbell (T5+), use
@@ -532,10 +535,10 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 
		 * mechanism.

		 */

		if (unlikely(q->bar2_addr == NULL)) {

			t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),

				     val | QID(q->cntxt_id));

			t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),

				     val | QID_V(q->cntxt_id));

		} else {

			writel(val | QID(q->bar2_qid),

			writel(val | QID_V(q->bar2_qid),

			       q->bar2_addr + SGE_UDB_KDOORBELL);



			/* This Write memory Barrier will force the write to
@@ -884,7 +887,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 
	 * doorbell mechanism; otherwise use the new BAR2 mechanism.

	 */

	if (unlikely(q->bar2_addr == NULL)) {

		u32 val = PIDX(n);

		u32 val = PIDX_V(n);

		unsigned long flags;



		/* For T4 we need to participate in the Doorbell Recovery
@@ -892,14 +895,14 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 
		 */

		spin_lock_irqsave(&q->db_lock, flags);

		if (!q->db_disabled)

			t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),

				     QID(q->cntxt_id) | val);

			t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),

				     QID_V(q->cntxt_id) | val);

		else

			q->db_pidx_inc += n;

		q->db_pidx = q->pidx;

		spin_unlock_irqrestore(&q->db_lock, flags);

	} else {

		u32 val = PIDX_T5(n);

		u32 val = PIDX_T5_V(n);



		/* T4 and later chips share the same PIDX field offset within

		 * the doorbell, but T5 and later shrank the field in order to
@@ -907,7 +910,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 
		 * large in the first place (14 bits) so we just use the T5

		 * and later limits and warn if a Queue ID is too large.

		 */

		WARN_ON(val & DBPRIO(1));

		WARN_ON(val & DBPRIO_F);



		/* If we're only writing a single TX Descriptor and we can use

		 * Inferred QID registers, we can use the Write Combining
@@ -923,7 +926,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 
				      (q->bar2_addr + SGE_UDB_WCDOORBELL),

				      wr);

		} else {

			writel(val | QID(q->bar2_qid),

			writel(val | QID_V(q->bar2_qid),

			       q->bar2_addr + SGE_UDB_KDOORBELL);

		}
@@ -2001,16 +2004,16 @@ static int napi_rx_handler(struct napi_struct *napi, int budget) 
	} else

		params = QINTR_TIMER_IDX(7);



	val = CIDXINC(work_done) | SEINTARM(params);

	val = CIDXINC_V(work_done) | SEINTARM_V(params);



	/* If we don't have access to the new User GTS (T5+), use the old

	 * doorbell mechanism; otherwise use the new BAR2 mechanism.

	 */

	if (unlikely(q->bar2_addr == NULL)) {

		t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS),

			     val | INGRESSQID((u32)q->cntxt_id));

		t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),

			     val | INGRESSQID_V((u32)q->cntxt_id));

	} else {

		writel(val | INGRESSQID(q->bar2_qid),

		writel(val | INGRESSQID_V(q->bar2_qid),

		       q->bar2_addr + SGE_UDB_GTS);

		wmb();

	}
@@ -2056,16 +2059,16 @@ static unsigned int process_intrq(struct adapter *adap) 
		rspq_next(q);

	}



	val =  CIDXINC(credits) | SEINTARM(q->intr_params);

	val =  CIDXINC_V(credits) | SEINTARM_V(q->intr_params);



	/* If we don't have access to the new User GTS (T5+), use the old

	 * doorbell mechanism; otherwise use the new BAR2 mechanism.

	 */

	if (unlikely(q->bar2_addr == NULL)) {

		t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),

			     val | INGRESSQID(q->cntxt_id));

		t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),

			     val | INGRESSQID_V(q->cntxt_id));

	} else {

		writel(val | INGRESSQID(q->bar2_qid),

		writel(val | INGRESSQID_V(q->bar2_qid),

		       q->bar2_addr + SGE_UDB_GTS);

		wmb();

	}
@@ -2770,8 +2773,8 @@ static int t4_sge_init_soft(struct adapter *adap) 
	 * process_responses() and that only packet data is going to the

	 * Free Lists.

	 */

	if ((t4_read_reg(adap, SGE_CONTROL) & RXPKTCPLMODE_MASK) !=

	    RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {

	if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) !=

	    RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {

		dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");

		return -EINVAL;

	}
@@ -2785,7 +2788,7 @@ static int t4_sge_init_soft(struct adapter *adap) 
	 * XXX meet our needs!

	 */

	#define READ_FL_BUF(x) \

		t4_read_reg(adap, SGE_FL_BUFFER_SIZE0+(x)*sizeof(u32))

		t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32))



	fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);

	fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
@@ -2839,11 +2842,11 @@ static int t4_sge_init_soft(struct adapter *adap) 
	s->timer_val[5] = core_ticks_to_us(adap,

		TIMERVALUE5_GET(timer_value_4_and_5));



	ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD);

	s->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold);

	s->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold);

	s->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold);

	s->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold);

	ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);

	s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);

	s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);

	s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);

	s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);



	return 0;

}
@@ -2856,8 +2859,7 @@ static int t4_sge_init_hard(struct adapter *adap) 
	 * Set up our basic SGE mode to deliver CPL messages to our Ingress

	 * Queue and Packet Date to the Free List.

	 */

	t4_set_reg_field(adap, SGE_CONTROL, RXPKTCPLMODE_MASK,

			 RXPKTCPLMODE_MASK);

	t4_set_reg_field(adap, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F);



	/*

	 * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
@@ -2887,22 +2889,22 @@ static int t4_sge_init_hard(struct adapter *adap) 
	s->fl_pg_order = FL_PG_ORDER;

	if (s->fl_pg_order)

		t4_write_reg(adap,

			     SGE_FL_BUFFER_SIZE0+RX_LARGE_PG_BUF*sizeof(u32),

			     SGE_FL_BUFFER_SIZE0_A+RX_LARGE_PG_BUF*sizeof(u32),

			     PAGE_SIZE << FL_PG_ORDER);

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_SMALL_MTU_BUF*sizeof(u32),

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_SMALL_MTU_BUF*sizeof(u32),

		     FL_MTU_SMALL_BUFSIZE(adap));

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_LARGE_MTU_BUF*sizeof(u32),

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_LARGE_MTU_BUF*sizeof(u32),

		     FL_MTU_LARGE_BUFSIZE(adap));



	/*

	 * Note that the SGE Ingress Packet Count Interrupt Threshold and

	 * Timer Holdoff values must be supplied by our caller.

	 */

	t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD,

		     THRESHOLD_0(s->counter_val[0]) |

		     THRESHOLD_1(s->counter_val[1]) |

		     THRESHOLD_2(s->counter_val[2]) |

		     THRESHOLD_3(s->counter_val[3]));

	t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD_A,

		     THRESHOLD_0_V(s->counter_val[0]) |

		     THRESHOLD_1_V(s->counter_val[1]) |

		     THRESHOLD_2_V(s->counter_val[2]) |

		     THRESHOLD_3_V(s->counter_val[3]));

	t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,

		     TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |

		     TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
@@ -2927,9 +2929,9 @@ int t4_sge_init(struct adapter *adap) 
	 * Ingress Padding Boundary and Egress Status Page Size are set up by

	 * t4_fixup_host_params().

	 */

	sge_control = t4_read_reg(adap, SGE_CONTROL);

	s->pktshift = PKTSHIFT_GET(sge_control);

	s->stat_len = (sge_control & EGRSTATUSPAGESIZE_MASK) ? 128 : 64;

	sge_control = t4_read_reg(adap, SGE_CONTROL_A);

	s->pktshift = PKTSHIFT_G(sge_control);

	s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;



	/* T4 uses a single control field to specify both the PCIe Padding and

	 * Packing Boundary.  T5 introduced the ability to specify these
@@ -2937,8 +2939,8 @@ int t4_sge_init(struct adapter *adap) 
	 * within Packed Buffer Mode is the maximum of these two

	 * specifications.

	 */

	ingpadboundary = 1 << (INGPADBOUNDARY_GET(sge_control) +

			       X_INGPADBOUNDARY_SHIFT);

	ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) +

			       INGPADBOUNDARY_SHIFT_X);

	if (is_t4(adap->params.chip)) {

		s->fl_align = ingpadboundary;

	} else {
@@ -2975,11 +2977,11 @@ int t4_sge_init(struct adapter *adap) 
	 * buffers and a new field which only applies to Packed Mode Free List

	 * buffers.

	 */

	sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL);

	sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A);

	if (is_t4(adap->params.chip))

		egress_threshold = EGRTHRESHOLD_GET(sge_conm_ctrl);

		egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl);

	else

		egress_threshold = EGRTHRESHOLDPACKING_GET(sge_conm_ctrl);

		egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);

	s->fl_starve_thres = 2*egress_threshold + 1;



	setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+60 −58
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include <linux/delay.h>

#include "cxgb4.h"

#include "t4_regs.h"

#include "t4_values.h"

#include "t4fw_api.h"



/**
@@ -1499,43 +1500,43 @@ static void sge_intr_handler(struct adapter *adapter) 
	u64 v;



	static const struct intr_info sge_intr_info[] = {

		{ ERR_CPL_EXCEED_IQE_SIZE,

		{ ERR_CPL_EXCEED_IQE_SIZE_F,

		  "SGE received CPL exceeding IQE size", -1, 1 },

		{ ERR_INVALID_CIDX_INC,

		{ ERR_INVALID_CIDX_INC_F,

		  "SGE GTS CIDX increment too large", -1, 0 },

		{ ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },

		{ DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },

		{ DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },

		{ ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },

		{ ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,

		{ ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },

		{ DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },

		{ DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },

		{ ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },

		{ ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,

		  "SGE IQID > 1023 received CPL for FL", -1, 0 },

		{ ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,

		{ ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,

		  0 },

		{ ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,

		{ ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,

		  0 },

		{ ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,

		{ ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,

		  0 },

		{ ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,

		{ ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,

		  0 },

		{ ERR_ING_CTXT_PRIO,

		{ ERR_ING_CTXT_PRIO_F,

		  "SGE too many priority ingress contexts", -1, 0 },

		{ ERR_EGR_CTXT_PRIO,

		{ ERR_EGR_CTXT_PRIO_F,

		  "SGE too many priority egress contexts", -1, 0 },

		{ INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },

		{ EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },

		{ INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },

		{ EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },

		{ 0 }

	};



	v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |

		((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);

	v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |

		((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);

	if (v) {

		dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",

				(unsigned long long)v);

		t4_write_reg(adapter, SGE_INT_CAUSE1, v);

		t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);

		t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);

		t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);

	}



	if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||

	if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info) ||

	    v != 0)

		t4_fatal_err(adapter);

}
@@ -2025,15 +2026,15 @@ void t4_intr_enable(struct adapter *adapter) 
{

	u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));



	t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |

		     ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |

		     ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |

		     ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |

		     ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |

		     ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |

		     ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |

		     DBFIFO_HP_INT | DBFIFO_LP_INT |

		     EGRESS_SIZE_ERR);

	t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |

		     ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |

		     ERR_DROPPED_DB_F | ERR_DATA_CPL_ON_HIGH_QID1_F |

		     ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |

		     ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |

		     ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |

		     ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F |

		     DBFIFO_HP_INT_F | DBFIFO_LP_INT_F |

		     EGRESS_SIZE_ERR_F);

	t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);

	t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);

}
@@ -3148,22 +3149,23 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 
	unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;

	unsigned int fl_align_log = fls(fl_align) - 1;



	t4_write_reg(adap, SGE_HOST_PAGE_SIZE,

		     HOSTPAGESIZEPF0(sge_hps) |

		     HOSTPAGESIZEPF1(sge_hps) |

		     HOSTPAGESIZEPF2(sge_hps) |

		     HOSTPAGESIZEPF3(sge_hps) |

		     HOSTPAGESIZEPF4(sge_hps) |

		     HOSTPAGESIZEPF5(sge_hps) |

		     HOSTPAGESIZEPF6(sge_hps) |

		     HOSTPAGESIZEPF7(sge_hps));

	t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,

		     HOSTPAGESIZEPF0_V(sge_hps) |

		     HOSTPAGESIZEPF1_V(sge_hps) |

		     HOSTPAGESIZEPF2_V(sge_hps) |

		     HOSTPAGESIZEPF3_V(sge_hps) |

		     HOSTPAGESIZEPF4_V(sge_hps) |

		     HOSTPAGESIZEPF5_V(sge_hps) |

		     HOSTPAGESIZEPF6_V(sge_hps) |

		     HOSTPAGESIZEPF7_V(sge_hps));



	if (is_t4(adap->params.chip)) {

		t4_set_reg_field(adap, SGE_CONTROL,

				 INGPADBOUNDARY_MASK |

				 EGRSTATUSPAGESIZE_MASK,

				 INGPADBOUNDARY(fl_align_log - 5) |

				 EGRSTATUSPAGESIZE(stat_len != 64));

		t4_set_reg_field(adap, SGE_CONTROL_A,

				 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |

				 EGRSTATUSPAGESIZE_F,

				 INGPADBOUNDARY_V(fl_align_log -

						  INGPADBOUNDARY_SHIFT_X) |

				 EGRSTATUSPAGESIZE_V(stat_len != 64));

	} else {

		/* T5 introduced the separation of the Free List Padding and

		 * Packing Boundaries.  Thus, we can select a smaller Padding
@@ -3193,11 +3195,11 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 
			fl_align = 64;

			fl_align_log = 6;

		}

		t4_set_reg_field(adap, SGE_CONTROL,

				 INGPADBOUNDARY_MASK |

				 EGRSTATUSPAGESIZE_MASK,

				 INGPADBOUNDARY(INGPCIEBOUNDARY_32B_X) |

				 EGRSTATUSPAGESIZE(stat_len != 64));

		t4_set_reg_field(adap, SGE_CONTROL_A,

				 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |

				 EGRSTATUSPAGESIZE_F,

				 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) |

				 EGRSTATUSPAGESIZE_V(stat_len != 64));

		t4_set_reg_field(adap, SGE_CONTROL2_A,

				 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),

				 INGPACKBOUNDARY_V(fl_align_log -
@@ -3224,12 +3226,12 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 
	 * Default Firmware Configuration File but we need to adjust it for

	 * this host's cache line size.

	 */

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,

		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,

		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)

		     & ~(fl_align-1));

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,

		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)

	t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,

		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)

		     & ~(fl_align-1));



	t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
@@ -4133,7 +4135,7 @@ int t4_init_sge_params(struct adapter *adapter) 


	/* Extract the SGE Page Size for our PF.

	 */

	hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE);

	hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);

	s_hps = (HOSTPAGESIZEPF0_S +

		 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->fn);

	sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
@@ -4142,10 +4144,10 @@ int t4_init_sge_params(struct adapter *adapter) 
	 */

	s_qpp = (QUEUESPERPAGEPF0_S +

		(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);

	qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF);

	sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_MASK);

	qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);

	sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);

	qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF);

	sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_MASK);

	sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);



	return 0;

}

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+288 −210

File changed.

Preview size limit exceeded, changes collapsed.