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Commit f02e0468 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm64-dt-for-v4.17' of... 

Merge tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Renesas ARM64 Based SoC DT Updates for v4.17" from Simon Horman:

* R-Car Gen3 boards and SoCs
  - Make phy-mode of EtherAVB a board-specific property.

    The SoC DTs file now uses "rgmii" and boards override this with
    "rgmii-txid" as appropriate. Previously "rgmii-txid" was used
    in SoC DTs but this did not describe that more sophiticated
    functionality is a board rather than SoC property.

* Condor board with R-Car V3H (r8a77980) SoC
  - Initial upstream support

* Condor board with R-Car V3H (r8a77980) SoC
  - Initial upstream support

* R-Car D3 (r8a77995)
  - Add I2C nodes and then describing the PCA9654 I/O expander connected to
    the I2C0 bus.

* Eagle board with R-Car V3M (r8a77970) SoC
  - Enable PFC support for configuring SCIF0 pins
    This uses PFC support added to the V3M DT

  - Describe EtherAVB PHY IRQ
    This uses support for GPIO added to the V3M DT

  - Enable I2C0 support

    Sergei Shtylyov says "The I2C0 bus is populated by ON Semiconductor
    PCA9653 I/O expander and Analog Devices ADV7511W HDMI transmitter (but
    we're only describing the former chip now)."

* R-Car V3M (r8a77970) SoCs
  - Add PFC support
  - Describe GPIO devices
  - Describe I2C devices
  - Srt subnodes of root node alphabetically to eas future maintence overhead

* Draak board with R-Car D3 (r8a77995) SoC
  - Enable SDHI2

    Wolfram Sang says "The single SDHI controller is connected to eMMC."

  - Enable DU

    Kieran Bingham says "Enable the DU, providing only the VGA output for
    now."

* R-Car D3 (r8a77995) and V3M (r8a77970) SoCs
  - Move nodes which have no reg property out of bus
    By deffinition the bus only has hardware with an address on the bus

  - Remove non-existing STBE region from EtherAVB
    Stream Buffer for EtherAVB-IF (STBE) is not present on these SoCs

* R-Car D3 (r8a77995) SoC
  - Add FCPV, VSP and DU support

    Kieran Bingham says "The r8a77995-d3 platform supports 3 VSP instances.
    One VSPBS can be used as a dual-input image blender, while two VSPD
    instances can be utilised as part of a display (DU) pipeline.

    Add support for these, along with their required FCPV nodes."

* Salvator-X and Salvator-XS boards with R-Car Gen3 SoCs
  - Add GPIO extender
    This is a basis for follow-up work to configure the GPIOs of the extender

* Salvator-X and Salvator-XS board with R-Car M3-N (r8a77965) SoC
  - Initial upstream support

* R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs
  - Add OPPs table for cpu devices
    This, along with recently upstreamed Z and Z2 clock support allows
    use of CPUFreq with both A57 and A53 CPUs.

  - Add thermal cooling management
    Allows the use of CPUFreq as a cooling device on A57 CPUs

  - Correct register size of thermal node

    Niklas Söderlund says "To be able to read fused calibration values from
    hardware the size of the register resource of TSC1 needs to be
    incremented to cover one more register which holds the information if
    the calibration values have been fused or not.

    Instead of increasing TSC1 size to the value from the datasheet update
    all TSC's size to the smallest granularity of the address decoder
    circuitry"

  - Fix register mappings on VSPs

    Kieran Bingham says "The VSPD includes a CLUT on RPF2. Ensure that the
    register space is mapped correctly to support this."

* R-Car H3 (r8a7795) SoC
  - Move SCIF node into alphabetical order to ease future maintenance overhead

  - Add IPMMU-PV1 device node

    This resolves an oversight when IPMMU nodes were added to the H3 DT.
    All IPMMU devices should now be described in DT.

  - Add missing SYS-DMAC2 dmas

    Geert Uytterhoeven says "On R-Car H3, on-chip peripheral modules that
    can make use of DMA are wired to either SYS-DMAC0 only, or to both
    SYS-DMAC1 and SYS-DMAC2.

    Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2],
    SCIF[0125], and I2C[0-2].  These were initially left out because early
    firmware versions prohibited using SYS-DMAC2.  This restriction has
    been lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25,
    2016)."

* tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (69 commits)
  arm64: dts: renesas: v3msk: add SCIF0 pins
  arm64: dts: renesas: r8a7795: Add missing SYS-DMAC2 dmas
  arm64: dts: renesas: r8a7795: Add IPMMU-PV1 device node
  arm64: dts: renesas: r8a77970: sort subnodes of root node alphabetically
  arm64: dts: renesas: eagle: add I2C0 support
  arm64: dts: renesas: r8a77970: add I2C support
  arm64: dts: renesas: r8a77965-salvator-xs: Add SoC name to file header
  arm64: dts: renesas: r8a77965: Add EtherAVB device node
  arm64: dts: renesas: r8a77970: Set EtherAVB phy mode to "rgmii"
  arm64: dts: renesas: r8a77995: Set EtherAVB phy mode to "rgmii"
  arm64: dts: renesas: r8a7795: Set EtherAVB phy mode to "rgmii"
  arm64: dts: renesas: r8a7796: Set EtherAVB phy mode to "rgmii"
  arm64: dts: renesas: v3msk: Override EtherAVB phy-mode
  arm64: dts: renesas: eagle: Override EtherAVB phy-mode
  arm64: dts: renesas: draak: Override EtherAVB phy-mode
  arm64: dts: renesas: ulcb: Override EtherAVB phy-mode
  arm64: dts: renesas: salvator-common: Override EtherAVB phy-mode
  arm64: dts: renesas: r8a77965: Add INTC-EX device node
  arm64: dts: renesas: r8a77965: Add IIC-DVFS device node
  arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-N
  ...
parents d45357e4 ca565be2

arch/arm64/Kconfig.platforms

+12 −0
Original line number Diff line number Diff line
@@ -190,12 +190,24 @@ config ARCH_R8A7796 
	help

	  This enables support for the Renesas R-Car M3-W SoC.



config ARCH_R8A77965

	bool "Renesas R-Car M3-N SoC Platform"

	depends on ARCH_RENESAS

	help

	  This enables support for the Renesas R-Car M3-N SoC.



config ARCH_R8A77970

	bool "Renesas R-Car V3M SoC Platform"

	depends on ARCH_RENESAS

	help

	  This enables support for the Renesas R-Car V3M SoC.



config ARCH_R8A77980

	bool "Renesas R-Car V3H SoC Platform"

	depends on ARCH_RENESAS

	help

	  This enables support for the Renesas R-Car V3H SoC.



config ARCH_R8A77995

	bool "Renesas R-Car D3 SoC Platform"

	depends on ARCH_RENESAS

arch/arm64/boot/dts/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -7,5 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb 
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb

dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb

dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb

dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb

dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb

dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb

dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb

arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 


	/delete-node/ mmu@febe0000;

	/delete-node/ mmu@fe980000;

	/delete-node/ mmu@fd950000;

	/delete-node/ mmu@fd960000;

	/delete-node/ mmu@fd970000;
@@ -80,7 +81,7 @@ 


	vspd3: vsp@fea38000 {

		compatible = "renesas,vsp2";

		reg = <0 0xfea38000 0 0x4000>;

		reg = <0 0xfea38000 0 0x8000>;

		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_MOD 620>;

		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+162 −32
Original line number Diff line number Diff line
@@ -41,6 +41,9 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a57_1: cpu@1 {
@@ -50,6 +53,9 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a57_2: cpu@2 {
@@ -59,6 +65,9 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a57_3: cpu@3 {
@@ -68,6 +77,9 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a53_0: cpu@100 {
@@ -77,6 +89,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_1: cpu@101 {
@@ -86,6 +100,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_2: cpu@102 {
@@ -95,6 +111,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_3: cpu@103 {
@@ -104,6 +122,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		L2_CA57: cache-controller-0 {
@@ -165,11 +185,59 @@ 
		clock-frequency = <0>;

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1700000000 {

			opp-hz = /bits/ 64 <1700000000>;

			opp-microvolt = <960000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

	};



	/* External PCIe clock - can be overridden by the board */
@@ -208,6 +276,13 @@ 
		method = "smc";

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	soc: soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;
@@ -470,6 +545,15 @@ 
			status = "disabled";

		};



		ipmmu_pv1: mmu@fd950000 {

			compatible = "renesas,ipmmu-r8a7795";

			reg = <0 0xfd950000 0 0x1000>;

			renesas,ipmmu-main = <&ipmmu_mm 7>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		ipmmu_pv2: mmu@fd960000 {

			compatible = "renesas,ipmmu-r8a7795";

			reg = <0 0xfd960000 0 0x1000>;
@@ -798,7 +882,7 @@ 
			clocks = <&cpg CPG_MOD 812>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			phy-mode = "rgmii-txid";

			phy-mode = "rgmii";

			iommus = <&ipmmu_ds0 16>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -992,8 +1076,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x31>, <&dmac1 0x30>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x31>, <&dmac1 0x30>,

			       <&dmac2 0x31>, <&dmac2 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 520>;

			status = "disabled";
@@ -1009,8 +1094,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x33>, <&dmac1 0x32>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x33>, <&dmac1 0x32>,

			       <&dmac2 0x33>, <&dmac2 0x32>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 519>;

			status = "disabled";
@@ -1026,8 +1112,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x35>, <&dmac1 0x34>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x35>, <&dmac1 0x34>,

			       <&dmac2 0x35>, <&dmac2 0x34>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 518>;

			status = "disabled";
@@ -1138,8 +1225,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,

			       <&dmac2 0x51>, <&dmac2 0x50>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 207>;

			status = "disabled";
@@ -1154,8 +1242,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,

			       <&dmac2 0x53>, <&dmac2 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 206>;

			status = "disabled";
@@ -1170,8 +1259,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x13>, <&dmac1 0x12>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x13>, <&dmac1 0x12>,

			       <&dmac2 0x13>, <&dmac2 0x12>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 310>;

			status = "disabled";
@@ -1218,8 +1308,9 @@ 
				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,

			       <&dmac2 0x5b>, <&dmac2 0x5a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 202>;

			status = "disabled";
@@ -1251,8 +1342,9 @@ 
			clocks = <&cpg CPG_MOD 931>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 931>;

			dmas = <&dmac1 0x91>, <&dmac1 0x90>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x91>, <&dmac1 0x90>,

			       <&dmac2 0x91>, <&dmac2 0x90>;

			dma-names = "tx", "rx", "tx", "rx";

			i2c-scl-internal-delay-ns = <110>;

			status = "disabled";

		};
@@ -1267,8 +1359,9 @@ 
			clocks = <&cpg CPG_MOD 930>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 930>;

			dmas = <&dmac1 0x93>, <&dmac1 0x92>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x93>, <&dmac1 0x92>,

			       <&dmac2 0x93>, <&dmac2 0x92>;

			dma-names = "tx", "rx", "tx", "rx";

			i2c-scl-internal-delay-ns = <6>;

			status = "disabled";

		};
@@ -1283,8 +1376,9 @@ 
			clocks = <&cpg CPG_MOD 929>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 929>;

			dmas = <&dmac1 0x95>, <&dmac1 0x94>;

			dma-names = "tx", "rx";

			dmas = <&dmac1 0x95>, <&dmac1 0x94>,

			       <&dmac2 0x95>, <&dmac2 0x94>;

			dma-names = "tx", "rx", "tx", "rx";

			i2c-scl-internal-delay-ns = <6>;

			status = "disabled";

		};
@@ -2143,7 +2237,7 @@ 


		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x4000>;

			reg = <0 0xfea20000 0 0x8000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2163,7 +2257,7 @@ 


		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x4000>;

			reg = <0 0xfea28000 0 0x8000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2183,7 +2277,7 @@ 


		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x4000>;

			reg = <0 0xfea30000 0 0x8000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2320,9 +2414,9 @@ 


		tsc: thermal@e6198000 {

			compatible = "renesas,r8a7795-thermal";

			reg = <0 0xe6198000 0 0x68>,

			      <0 0xe61a0000 0 0x5c>,

			      <0 0xe61a8000 0 0x5c>;

			reg = <0 0xe6198000 0 0x100>,

			      <0 0xe61a0000 0 0x100>,

			      <0 0xe61a8000 0 0x100>;

			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -2357,12 +2451,24 @@ 
			thermal-sensors = <&tsc 0>;



			trips {

				sensor1_passive: sensor1-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor1_crit: sensor1-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor1_passive>;

					cooling-device = <&a57_0 4 4>;

				};

			};

		};



		sensor_thermal2: sensor-thermal2 {
@@ -2371,12 +2477,24 @@ 
			thermal-sensors = <&tsc 1>;



			trips {

				sensor2_passive: sensor2-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor2_crit: sensor2-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor2_passive>;

					cooling-device = <&a57_0 4 4>;

				};

			};

		};



		sensor_thermal3: sensor-thermal3 {
@@ -2385,12 +2503,24 @@ 
			thermal-sensors = <&tsc 2>;



			trips {

				sensor3_passive: sensor3-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor3_crit: sensor3-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor3_passive>;

					cooling-device = <&a57_0 4 4>;

				};

			};

		};

	};

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+123 −7
Original line number Diff line number Diff line
@@ -71,6 +71,9 @@ 
			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a57_1: cpu@1 {
@@ -80,6 +83,9 @@ 
			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

		};



		a53_0: cpu@100 {
@@ -89,6 +95,8 @@ 
			power-domains = <&sysc R8A7796_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_1: cpu@101 {
@@ -98,6 +106,8 @@ 
			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_2: cpu@102 {
@@ -107,6 +117,8 @@ 
			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_3: cpu@103 {
@@ -116,6 +128,8 @@ 
			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		L2_CA57: cache-controller-0 {
@@ -147,6 +161,72 @@ 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1700000000 {

			opp-hz = /bits/ 64 <1700000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <960000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1300000000 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

	};



	/* External PCIe clock - can be overridden by the board */

	pcie_bus_clk: pcie_bus {

		compatible = "fixed-clock";
@@ -894,7 +974,7 @@ 
			clocks = <&cpg CPG_MOD 812>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			phy-mode = "rgmii-txid";

			phy-mode = "rgmii";

			iommus = <&ipmmu_ds0 16>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -1561,9 +1641,9 @@ 


		tsc: thermal@e6198000 {

			compatible = "renesas,r8a7796-thermal";

			reg = <0 0xe6198000 0 0x68>,

			      <0 0xe61a0000 0 0x5c>,

			      <0 0xe61a8000 0 0x5c>;

			reg = <0 0xe6198000 0 0x100>,

			      <0 0xe61a0000 0 0x100>,

			      <0 0xe61a8000 0 0x100>;

			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -1839,7 +1919,7 @@ 


		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x4000>;

			reg = <0 0xfea20000 0 0x8000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1859,7 +1939,7 @@ 


		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x4000>;

			reg = <0 0xfea28000 0 0x8000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1879,7 +1959,7 @@ 


		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x4000>;

			reg = <0 0xfea30000 0 0x8000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1998,12 +2078,24 @@ 
			thermal-sensors = <&tsc 0>;



			trips {

				sensor1_passive: sensor1-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor1_crit: sensor1-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor1_passive>;

					cooling-device = <&a57_0 5 5>;

				};

			};

		};



		sensor_thermal2: sensor-thermal2 {
@@ -2012,12 +2104,24 @@ 
			thermal-sensors = <&tsc 1>;



			trips {

				sensor2_passive: sensor2-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor2_crit: sensor2-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor2_passive>;

					cooling-device = <&a57_0 5 5>;

				};

			};

		};



		sensor_thermal3: sensor-thermal3 {
@@ -2026,12 +2130,24 @@ 
			thermal-sensors = <&tsc 2>;



			trips {

				sensor3_passive: sensor3-passive {

					temperature = <95000>;

					hysteresis = <2000>;

					type = "passive";

				};

				sensor3_crit: sensor3-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&sensor3_passive>;

					cooling-device = <&a57_0 5 5>;

				};

			};

		};

	};