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Commit d45357e4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-4.17-arm64-dt' of... 

Merge tag 'tegra-for-4.17-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

Pull "arm64: tegra: Device tree changes for v4.17-rc1" from Thierry Reding:

Adds initial support for the P2972-0000 development board based on
Tegra194 and enables the AHCI controller on Jetson TX1.

* tag 'tegra-for-4.17-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Enable AHCI on Jetson TX1
  arm64: tegra: Add SATA node for Tegra210
  arm64: tegra: Add device tree for the Tegra194 P2972-0000 board
  arm64: tegra: Add Tegra194 chip device tree
parents b2fc2640 0f2754ce

arch/arm64/boot/dts/nvidia/Makefile

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@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb 
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb

dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb

dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb

dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb

arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi

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// SPDX-License-Identifier: GPL-2.0

#include "tegra194.dtsi"



#include <dt-bindings/mfd/max77620.h>



/ {

	model = "NVIDIA Tegra194 P2888 Processor Module";

	compatible = "nvidia,p2888", "nvidia,tegra194";



	aliases {

		sdhci0 = "/cbb/sdhci@3460000";

		sdhci1 = "/cbb/sdhci@3400000";

		serial0 = &uartb;

		i2c0 = "/bpmp/i2c";

		i2c1 = "/cbb/i2c@3160000";

		i2c2 = "/cbb/i2c@c240000";

		i2c3 = "/cbb/i2c@3180000";

		i2c4 = "/cbb/i2c@3190000";

		i2c5 = "/cbb/i2c@31c0000";

		i2c6 = "/cbb/i2c@c250000";

		i2c7 = "/cbb/i2c@31e0000";

	};



	chosen {

		bootargs = "console=ttyS0,115200n8";

		stdout-path = "serial0:115200n8";

	};



	cbb {

		serial@3110000 {

			status = "okay";

		};



		/* SDMMC1 (SD/MMC) */

		sdhci@3400000 {

/*

			cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;

*/

		};



		/* SDMMC4 (eMMC) */

		sdhci@3460000 {

			status = "okay";

			bus-width = <8>;

			non-removable;



			vqmmc-supply = <&vdd_1v8ls>;

			vmmc-supply = <&vdd_emmc_3v3>;

		};



		pmc@c360000 {

			nvidia,invert-interrupt;

		};

	};



	bpmp {

		i2c {

			status = "okay";



			pmic: pmic@3c {

				compatible = "maxim,max20024";

				reg = <0x3c>;



				interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

				#interrupt-cells = <2>;

				interrupt-controller;



				#gpio-cells = <2>;

				gpio-controller;



				pinctrl-names = "default";

				pinctrl-0 = <&max20024_default>;



				max20024_default: pinmux {

					gpio0 {

						pins = "gpio0";

						function = "gpio";

					};



					gpio1 {

						pins = "gpio1";

						function = "fps-out";

						maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;

					};



					gpio2 {

						pins = "gpio2";

						function = "fps-out";

						maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;

					};



					gpio3 {

						pins = "gpio3";

						function = "fps-out";

						maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;

					};



					gpio4 {

						pins = "gpio4";

						function = "32k-out1";

						drive-push-pull = <1>;

					};



					gpio6 {

						pins = "gpio6";

						function = "gpio";

						drive-push-pull = <1>;

					};



					gpio7 {

						pins = "gpio7";

						function = "gpio";

						drive-push-pull = <0>;

					};

				};



				fps {

					fps0 {

						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;

						maxim,shutdown-fps-time-period-us = <640>;

					};



					fps1 {

						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;

						maxim,shutdown-fps-time-period-us = <640>;

						maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;

					};



					fps2 {

						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;

						maxim,shutdown-fps-time-period-us = <640>;

					};

				};



				regulators {

					in-sd0-supply = <&vdd_5v0_sys>;

					in-sd1-supply = <&vdd_5v0_sys>;

					in-sd2-supply = <&vdd_5v0_sys>;

					in-sd3-supply = <&vdd_5v0_sys>;

					in-sd4-supply = <&vdd_5v0_sys>;



					in-ldo0-1-supply = <&vdd_5v0_sys>;

					in-ldo2-supply = <&vdd_5v0_sys>;

					in-ldo3-5-supply = <&vdd_5v0_sys>;

					in-ldo4-6-supply = <&vdd_5v0_sys>;

					in-ldo7-8-supply = <&vdd_1v8ls>;



					sd0 {

						regulator-name = "VDD_1V0";

						regulator-min-microvolt = <1000000>;

						regulator-max-microvolt = <1000000>;

						regulator-always-on;

						regulator-boot-on;

					};



					sd1 {

						regulator-name = "VDD_1V8HS";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;

						regulator-boot-on;

					};



					vdd_1v8ls: sd2 {

						regulator-name = "VDD_1V8LS";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;

						regulator-boot-on;

					};



					sd3 {

						regulator-name = "VDD_1V8AO";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;

						regulator-boot-on;

					};



					sd4 {

						regulator-name = "VDD_DDR_1V1";

						regulator-min-microvolt = <1100000>;

						regulator-max-microvolt = <1100000>;

						regulator-always-on;

						regulator-boot-on;

					};



					ldo0 {

						regulator-name = "VDD_RTC";

						regulator-min-microvolt = <800000>;

						regulator-max-microvolt = <800000>;

						regulator-always-on;

						regulator-boot-on;

					};



					ldo2 {

						regulator-name = "VDD_AO_3V3";

						regulator-min-microvolt = <3300000>;

						regulator-max-microvolt = <3300000>;

						regulator-always-on;

						regulator-boot-on;

					};



					vdd_emmc_3v3: ldo3 {

						regulator-name = "VDD_EMMC_3V3";

						regulator-min-microvolt = <3300000>;

						regulator-max-microvolt = <3300000>;

					};



					ldo5 {

						regulator-name = "VDD_USB_3V3";

						regulator-min-microvolt = <3300000>;

						regulator-max-microvolt = <3300000>;

					};



					ldo6 {

						regulator-name = "VDD_SDIO_3V3";

						regulator-min-microvolt = <3300000>;

						regulator-max-microvolt = <3300000>;

					};



					ldo7 {

						regulator-name = "VDD_CSI_1V2";

						regulator-min-microvolt = <1200000>;

						regulator-max-microvolt = <1200000>;

					};

				};

			};

		};

	};



	regulators {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		vdd_5v0_sys: regulator@0 {

			compatible = "regulator-fixed";

			reg = <0>;



			regulator-name = "VIN_SYS_5V0";

			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;

			regulator-always-on;

			regulator-boot-on;

		};

	};

};

arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

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// SPDX-License-Identifier: GPL-2.0

/dts-v1/;



#include "tegra194-p2888.dtsi"



/ {

	model = "NVIDIA Tegra194 P2972-0000 Development Board";

	compatible = "nvidia,p2972-0000", "nvidia,tegra194";



	cbb {

		/* SDMMC1 (SD/MMC) */

		sdhci@3400000 {

			status = "okay";

		};

	};

};

arch/arm64/boot/dts/nvidia/tegra194.dtsi

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// SPDX-License-Identifier: GPL-2.0

#include <dt-bindings/clock/tegra194-clock.h>

#include <dt-bindings/gpio/tegra194-gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/tegra186-hsp.h>

#include <dt-bindings/reset/tegra194-reset.h>



/ {

	compatible = "nvidia,tegra194";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	/* control backbone */

	cbb {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x0 0x40000000>;



		uarta: serial@3100000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03100000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTA>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTA>;

			reset-names = "serial";

			status = "disabled";

		};



		uartb: serial@3110000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03110000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTB>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTB>;

			reset-names = "serial";

			status = "disabled";

		};



		uartd: serial@3130000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03130000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTD>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTD>;

			reset-names = "serial";

			status = "disabled";

		};



		uarte: serial@3140000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03140000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTE>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTE>;

			reset-names = "serial";

			status = "disabled";

		};



		uartf: serial@3150000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03150000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTF>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTF>;

			reset-names = "serial";

			status = "disabled";

		};



		gen1_i2c: i2c@3160000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x03160000 0x10000>;

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C1>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C1>;

			reset-names = "i2c";

			status = "disabled";

		};



		uarth: serial@3170000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x03170000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTH>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTH>;

			reset-names = "serial";

			status = "disabled";

		};



		cam_i2c: i2c@3180000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x03180000 0x10000>;

			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C3>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C3>;

			reset-names = "i2c";

			status = "disabled";

		};



		/* shares pads with dpaux1 */

		dp_aux_ch1_i2c: i2c@3190000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x03190000 0x10000>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C4>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C4>;

			reset-names = "i2c";

			status = "disabled";

		};



		/* shares pads with dpaux0 */

		dp_aux_ch0_i2c: i2c@31b0000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x031b0000 0x10000>;

			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C6>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C6>;

			reset-names = "i2c";

			status = "disabled";

		};



		gen7_i2c: i2c@31c0000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x031c0000 0x10000>;

			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C7>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C7>;

			reset-names = "i2c";

			status = "disabled";

		};



		gen9_i2c: i2c@31e0000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x031e0000 0x10000>;

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C9>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C9>;

			reset-names = "i2c";

			status = "disabled";

		};



		sdmmc1: sdhci@3400000 {

			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";

			reg = <0x03400000 0x10000>;

			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_SDMMC1>;

			clock-names = "sdhci";

			resets = <&bpmp TEGRA194_RESET_SDMMC1>;

			reset-names = "sdhci";

			status = "disabled";

		};



		sdmmc3: sdhci@3440000 {

			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";

			reg = <0x03440000 0x10000>;

			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_SDMMC3>;

			clock-names = "sdhci";

			resets = <&bpmp TEGRA194_RESET_SDMMC3>;

			reset-names = "sdhci";

			status = "disabled";

		};



		sdmmc4: sdhci@3460000 {

			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";

			reg = <0x03460000 0x10000>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_SDMMC4>;

			clock-names = "sdhci";

			resets = <&bpmp TEGRA194_RESET_SDMMC4>;

			reset-names = "sdhci";

			status = "disabled";

		};



		gic: interrupt-controller@3881000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x03881000 0x1000>,

			      <0x03882000 0x2000>,

			      <0x03884000 0x2000>,

			      <0x03886000 0x2000>;

			interrupts = <GIC_PPI 9

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupt-parent = <&gic>;

		};



		hsp_top0: hsp@3c00000 {

			compatible = "nvidia,tegra186-hsp";

			reg = <0x03c00000 0xa0000>;

			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "doorbell";

			#mbox-cells = <2>;

		};



		gen2_i2c: i2c@c240000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x0c240000 0x10000>;

			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C2>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C2>;

			reset-names = "i2c";

			status = "disabled";

		};



		gen8_i2c: i2c@c250000 {

			compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";

			reg = <0x0c250000 0x10000>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA194_CLK_I2C8>;

			clock-names = "div-clk";

			resets = <&bpmp TEGRA194_RESET_I2C8>;

			reset-names = "i2c";

			status = "disabled";

		};



		uartc: serial@c280000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x0c280000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTC>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTC>;

			reset-names = "serial";

			status = "disabled";

		};



		uartg: serial@c290000 {

			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";

			reg = <0x0c290000 0x40>;

			reg-shift = <2>;

			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_UARTG>;

			clock-names = "serial";

			resets = <&bpmp TEGRA194_RESET_UARTG>;

			reset-names = "serial";

			status = "disabled";

		};



		pmc@c360000 {

			compatible = "nvidia,tegra194-pmc";

			reg = <0x0c360000 0x10000>,

			      <0x0c370000 0x10000>,

			      <0x0c380000 0x10000>,

			      <0x0c390000 0x10000>,

			      <0x0c3a0000 0x10000>;

			reg-names = "pmc", "wake", "aotag", "scratch", "misc";

		};

	};



	sysram@40000000 {

		compatible = "nvidia,tegra194-sysram", "mmio-sram";

		reg = <0x0 0x40000000 0x0 0x50000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x40000000 0x50000>;



		cpu_bpmp_tx: shmem@4e000 {

			compatible = "nvidia,tegra194-bpmp-shmem";

			reg = <0x4e000 0x1000>;

			label = "cpu-bpmp-tx";

			pool;

		};



		cpu_bpmp_rx: shmem@4f000 {

			compatible = "nvidia,tegra194-bpmp-shmem";

			reg = <0x4f000 0x1000>;

			label = "cpu-bpmp-rx";

			pool;

		};

	};



	bpmp: bpmp {

		compatible = "nvidia,tegra186-bpmp";

		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB

				    TEGRA_HSP_DB_MASTER_BPMP>;

		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		#power-domain-cells = <1>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";

			nvidia,bpmp-bus-id = <5>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		bpmp_thermal: thermal {

			compatible = "nvidia,tegra186-bpmp-thermal";

			#thermal-sensor-cells = <1>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

	};

};

arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -1325,6 +1325,11 @@ 
		status = "okay";

	};



	sata@70020000 {

		status = "okay";

		phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;

	};



	padctl@7009f000 {

		status = "okay";