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Commit e3f33d46 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
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drm/i915: add L3 bank clock gating disable on VLV 

Prevents a possible hang: WaDisableL3Bank2xClockGate.

v2: only apply to VLV, IVB doesn't need this anymore

References: https://bugs.freedesktop.org/show_bug.cgi?id=50245


Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6edaa7fc

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -4043,6 +4043,9 @@ 
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)



#define GEN7_UCGCTL4				0x940c

#define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)



#define GEN6_RPNSWREQ				0xA008

#define   GEN6_TURBO_DISABLE			(1<<31)

#define   GEN6_FREQUENCY(x)			((x)<<25)

drivers/gpu/drm/i915/intel_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -3517,6 +3517,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |