Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6edaa7fc authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: add TDL unit clock gating disable for VLV 

Another required workaround for a potential hang:
WaDisableTDLUnitClockGating.

v2: only apply this to VLV, IVB doesn't need it anymore (Eugeni)

References: https://bugs.freedesktop.org/show_bug.cgi?id=50245


Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b4ae3f22

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4038,6 +4038,7 @@ 


#define GEN6_UCGCTL2				0x9404

# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)

# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)

drivers/gpu/drm/i915/intel_pm.c

+1 −0
Original line number Diff line number Diff line
@@ -3512,6 +3512,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	 */

	I915_WRITE(GEN6_UCGCTL2,

		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |

		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);