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Commit e3ab6013 authored by Tero Kristo's avatar Tero Kristo Committed by Paul Walmsley
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ARM: OMAP3: clock: add support for dpll4_set_rate_and_parent 



Expand the support of omap4 per-dpll to provide set_rate_and_parent.
This is required for proper behavior of clk_change_rate with
determine_rate support.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 83501ff0

arch/arm/mach-omap2/clock3xxx.c

+36 −0
Original line number Original line Diff line number Diff line
@@ -38,6 +38,18 @@ 




/* needed by omap3_core_dpll_m2_set_rate() */

/* needed by omap3_core_dpll_m2_set_rate() */

struct clk *sdrc_ick_p, *arm_fck_p;

struct clk *sdrc_ick_p, *arm_fck_p;



/**

 * omap3_dpll4_set_rate - set rate for omap3 per-dpll

 * @hw: clock to change

 * @rate: target rate for clock

 * @parent_rate: rate of the parent clock

 *

 * Check if the current SoC supports the per-dpll reprogram operation

 * or not, and then do the rate change if supported. Returns -EINVAL

 * if not supported, 0 for success, and potential error codes from the

 * clock rate change.

 */

int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,

int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

				unsigned long parent_rate)

{

{
@@ -54,6 +66,30 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, 
	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);

	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);

}

}





/**

 * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll

 * @hw: clock to change

 * @rate: target rate for clock

 * @parent_rate: rate of the parent clock

 * @index: parent index, 0 - reference clock, 1 - bypass clock

 *

 * Check if the current SoC support the per-dpll reprogram operation

 * or not, and then do the rate + parent change if supported. Returns

 * -EINVAL if not supported, 0 for success, and potential error codes

 * from the clock rate change.

 */

int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,

				    unsigned long parent_rate, u8 index)

{

	if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {

		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");

		return -EINVAL;

	}



	return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,

						      index);

}



void __init omap3_clk_lock_dpll5(void)

void __init omap3_clk_lock_dpll5(void)

{

{

	struct clk *dpll5_clk;

	struct clk *dpll5_clk;

include/linux/clk/ti.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -291,6 +291,8 @@ int omap2_clk_disable_autoidle_all(void); 
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,

int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,

			 unsigned long parent_rate);

			 unsigned long parent_rate);

int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,

				    unsigned long parent_rate, u8 index);

int omap2_dflt_clk_enable(struct clk_hw *hw);

int omap2_dflt_clk_enable(struct clk_hw *hw);

void omap2_dflt_clk_disable(struct clk_hw *hw);

void omap2_dflt_clk_disable(struct clk_hw *hw);

int omap2_dflt_clk_is_enabled(struct clk_hw *hw);

int omap2_dflt_clk_is_enabled(struct clk_hw *hw);