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Commit 83501ff0 authored by Tero Kristo's avatar Tero Kristo Committed by Paul Walmsley
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ARM: OMAP4: clock: add support for determine_rate for omap4 regm4xen DPLL 



Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock
type is wrong. This patch adds basic functionality for determine_rate
for this clock type which will be taken into use in the patches following
later.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent d539efa3

arch/arm/mach-omap2/dpll44xx.c

+41 −0
Original line number Diff line number Diff line
@@ -207,3 +207,44 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 


	return dd->last_rounded_rate;

}



/**

 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL

 * @hw: pointer to the clock to determine rate for

 * @rate: target rate for the DPLL

 * @best_parent_rate: pointer for returning best parent rate

 * @best_parent_clk: pointer for returning best parent clock

 *

 * Determines which DPLL mode to use for reaching a desired rate.

 * Checks whether the DPLL shall be in bypass or locked mode, and if

 * locked, calculates the M,N values for the DPLL via round-rate.

 * Returns a positive clock rate with success, negative error value

 * in failure.

 */

long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,

					unsigned long *best_parent_rate,

					struct clk **best_parent_clk)

{

	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	struct dpll_data *dd;



	if (!hw || !rate)

		return -EINVAL;



	dd = clk->dpll_data;

	if (!dd)

		return -EINVAL;



	if (__clk_get_rate(dd->clk_bypass) == rate &&

	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {

		*best_parent_clk = dd->clk_bypass;

	} else {

		rate = omap4_dpll_regm4xen_round_rate(hw, rate,

						      best_parent_rate);

		*best_parent_clk = dd->clk_ref;

	}



	*best_parent_rate = rate;



	return rate;

}

include/linux/clk/ti.h

+4 −0
Original line number Diff line number Diff line
@@ -270,6 +270,10 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,

				    unsigned long target_rate,

				    unsigned long *parent_rate);

long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,

					unsigned long rate,

					unsigned long *best_parent_rate,

					struct clk **best_parent_clk);

u8 omap2_init_dpll_parent(struct clk_hw *hw);

unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);

long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,