Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit de90c5ce authored by Andi Kleen's avatar Andi Kleen Committed by Andi Kleen
Browse files

[PATCH] i386: Enable bank 0 on non K7 Athlon 



As a bug workaround bank 0 on K7s is normally disabled, but no need
to do that on other AMD CPUs.

Cc: davej@redhat.com

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent d479d2cc

arch/i386/kernel/cpu/mcheck/k7.c

+7 −3
Original line number Original line Diff line number Diff line
@@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) 
	nr_mce_banks = l & 0xff;

	nr_mce_banks = l & 0xff;





	/* Clear status for MC index 0 separately, we don't touch CTL,

	/* Clear status for MC index 0 separately, we don't touch CTL,

	 * as some Athlons cause spurious MCEs when its enabled. */

	 * as some K7 Athlons cause spurious MCEs when its enabled. */

	if (boot_cpu_data.x86 == 6) {

		wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);

		wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);

	for (i=1; i<nr_mce_banks; i++) {

		i = 1;

	} else

		i = 0;

	for (; i<nr_mce_banks; i++) {

		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);

		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);

		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);

		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);

	}

	}