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Commit da1677b0 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: Disintegrate arcregs.h 



* Move the various sub-system defines/types into relevant files/functions
  (reduces compilation time)

* move CPU specific stuff out of asm/tlb.h into asm/mmu.h

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 18437347

arch/arc/include/asm/arcregs.h

+0 −116
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ 
#define ARC_REG_PERIBASE_BCR	0x69

#define ARC_REG_FP_BCR		0x6B	/* Single-Precision FPU */

#define ARC_REG_DPFP_BCR	0x6C	/* Dbl Precision FPU */

#define ARC_REG_MMU_BCR		0x6f

#define ARC_REG_DCCM_BCR	0x74	/* DCCM Present + SZ */

#define ARC_REG_TIMERS_BCR	0x75

#define ARC_REG_ICCM_BCR	0x78
@@ -34,22 +33,12 @@ 
#define ARC_REG_D_UNCACH_BCR	0x6A



/* status32 Bits Positions */

#define STATUS_H_BIT		0	/* CPU Halted */

#define STATUS_E1_BIT		1	/* Int 1 enable */

#define STATUS_E2_BIT		2	/* Int 2 enable */

#define STATUS_A1_BIT		3	/* Int 1 active */

#define STATUS_A2_BIT		4	/* Int 2 active */

#define STATUS_AE_BIT		5	/* Exception active */

#define STATUS_DE_BIT		6	/* PC is in delay slot */

#define STATUS_U_BIT		7	/* User/Kernel mode */

#define STATUS_L_BIT		12	/* Loop inhibit */



/* These masks correspond to the status word(STATUS_32) bits */

#define STATUS_H_MASK		(1<<STATUS_H_BIT)

#define STATUS_E1_MASK		(1<<STATUS_E1_BIT)

#define STATUS_E2_MASK		(1<<STATUS_E2_BIT)

#define STATUS_A1_MASK		(1<<STATUS_A1_BIT)

#define STATUS_A2_MASK		(1<<STATUS_A2_BIT)

#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)

#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)

#define STATUS_U_MASK		(1<<STATUS_U_BIT)
@@ -87,86 +76,7 @@ 
/* Auxiliary registers */

#define AUX_IDENTITY		4

#define AUX_INTR_VEC_BASE	0x25

#define AUX_IRQ_LEV		0x200	/* IRQ Priority: L1 or L2 */

#define AUX_IRQ_HINT		0x201	/* For generating Soft Interrupts */

#define AUX_IRQ_LV12		0x43	/* interrupt level register */



#define AUX_IENABLE		0x40c

#define AUX_ITRIGGER		0x40d

#define AUX_IPULSE		0x415



/* Timer related Aux registers */

#define ARC_REG_TIMER0_LIMIT	0x23	/* timer 0 limit */

#define ARC_REG_TIMER0_CTRL	0x22	/* timer 0 control */

#define ARC_REG_TIMER0_CNT	0x21	/* timer 0 count */

#define ARC_REG_TIMER1_LIMIT	0x102	/* timer 1 limit */

#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */

#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */



#define TIMER_CTRL_IE		(1 << 0) /* Interupt when Count reachs limit */

#define TIMER_CTRL_NH		(1 << 1) /* Count only when CPU NOT halted */



/* MMU Management regs */

#define ARC_REG_TLBPD0		0x405

#define ARC_REG_TLBPD1		0x406

#define ARC_REG_TLBINDEX	0x407

#define ARC_REG_TLBCOMMAND	0x408

#define ARC_REG_PID		0x409

#define ARC_REG_SCRATCH_DATA0	0x418



/* Bits in MMU PID register */

#define MMU_ENABLE		(1 << 31)	/* Enable MMU for process */



/* Error code if probe fails */

#define TLB_LKUP_ERR		0x80000000



/* TLB Commands */

#define TLBWrite    0x1

#define TLBRead     0x2

#define TLBGetIndex 0x3

#define TLBProbe    0x4



#if (CONFIG_ARC_MMU_VER >= 2)

#define TLBWriteNI  0x5		/* write JTLB without inv uTLBs */

#define TLBIVUTLB   0x6		/* explicitly inv uTLBs */

#else

#undef TLBWriteNI		/* These cmds don't exist on older MMU */

#undef TLBIVUTLB

#endif



/* Instruction cache related Auxiliary registers */

#define ARC_REG_IC_BCR		0x77	/* Build Config reg */

#define ARC_REG_IC_IVIC		0x10

#define ARC_REG_IC_CTRL		0x11

#define ARC_REG_IC_IVIL		0x19

#if (CONFIG_ARC_MMU_VER > 2)

#define ARC_REG_IC_PTAG		0x1E

#endif



/* Bit val in IC_CTRL */

#define IC_CTRL_CACHE_DISABLE   0x1



/* Data cache related Auxiliary registers */

#define ARC_REG_DC_BCR		0x72

#define ARC_REG_DC_IVDC		0x47

#define ARC_REG_DC_CTRL		0x48

#define ARC_REG_DC_IVDL		0x4A

#define ARC_REG_DC_FLSH		0x4B

#define ARC_REG_DC_FLDL		0x4C

#if (CONFIG_ARC_MMU_VER > 2)

#define ARC_REG_DC_PTAG		0x5C

#endif



/* Bit val in DC_CTRL */

#define DC_CTRL_INV_MODE_FLUSH  0x40

#define DC_CTRL_FLUSH_STATUS    0x100



/* MMU Management regs */

#define ARC_REG_PID		0x409

#define ARC_REG_SCRATCH_DATA0	0x418



/* Bits in MMU PID register */

#define MMU_ENABLE		(1 << 31)	/* Enable MMU for process */



/*

 * Floating Pt Registers
@@ -293,24 +203,6 @@ struct bcr_identity { 
#endif

};



struct bcr_mmu_1_2 {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;

#else

	unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;

#endif

};



struct bcr_mmu_3 {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,

		     u_itlb:4, u_dtlb:4;

#else

	unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,

		     ways:4, ver:8;

#endif

};



#define EXTN_SWAP_VALID     0x1

#define EXTN_NORM_VALID     0x2

#define EXTN_MINMAX_VALID   0x2
@@ -343,14 +235,6 @@ struct bcr_extn_xymem { 
#endif

};



struct bcr_cache {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;

#else

	unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;

#endif

};



struct bcr_perip {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int start:8, pad2:8, sz:8, pad:8;

arch/arc/include/asm/cache.h

+9 −10
Original line number Diff line number Diff line
@@ -9,8 +9,6 @@ 
#ifndef __ARC_ASM_CACHE_H

#define __ARC_ASM_CACHE_H



#include <asm/mmu.h>	/* some of cache registers depend on MMU ver */



/* In case $$ not config, setup a dummy number for rest of kernel */

#ifndef CONFIG_ARC_CACHE_LINE_SHIFT

#define L1_CACHE_SHIFT		6
@@ -36,6 +34,13 @@ 
#define is_not_cache_aligned(p)	((unsigned long)p & (~DCACHE_LINE_MASK))

#endif



/*

 * ARC700 doesn't cache any access in top 256M.

 * Ideal for wiring memory mapped peripherals as we don't need to do

 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers

 */

#define ARC_UNCACHED_ADDR_SPACE	0xc0000000



#ifndef __ASSEMBLY__



/* Uncached access macros */
@@ -59,16 +64,10 @@ 


#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES



/*

 * ARC700 doesn't cache any access in top 256M.

 * Ideal for wiring memory mapped peripherals as we don't need to do

 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers

 */

#define ARC_UNCACHED_ADDR_SPACE	0xc0000000



extern void arc_cache_init(void);

extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);

extern void __init read_decode_cache_bcr(void);

#endif



#endif	/* !__ASSEMBLY__ */



#endif /* _ASM_CACHE_H */

arch/arc/include/asm/irqflags.h

+20 −0
Original line number Diff line number Diff line
@@ -19,6 +19,26 @@ 


#include <asm/arcregs.h>



/* status32 Reg bits related to Interrupt Handling */

#define STATUS_E1_BIT		1	/* Int 1 enable */

#define STATUS_E2_BIT		2	/* Int 2 enable */

#define STATUS_A1_BIT		3	/* Int 1 active */

#define STATUS_A2_BIT		4	/* Int 2 active */



#define STATUS_E1_MASK		(1<<STATUS_E1_BIT)

#define STATUS_E2_MASK		(1<<STATUS_E2_BIT)

#define STATUS_A1_MASK		(1<<STATUS_A1_BIT)

#define STATUS_A2_MASK		(1<<STATUS_A2_BIT)



/* Other Interrupt Handling related Aux regs */

#define AUX_IRQ_LEV		0x200	/* IRQ Priority: L1 or L2 */

#define AUX_IRQ_HINT		0x201	/* For generating Soft Interrupts */

#define AUX_IRQ_LV12		0x43	/* interrupt level register */



#define AUX_IENABLE		0x40c

#define AUX_ITRIGGER		0x40d

#define AUX_IPULSE		0x415



#ifndef __ASSEMBLY__



/******************************************************************

arch/arc/include/asm/mmu.h

+36 −0
Original line number Diff line number Diff line
@@ -17,6 +17,32 @@ 
#define CONFIG_ARC_MMU_VER 3

#endif



/* MMU Management regs */

#define ARC_REG_MMU_BCR		0x06f

#define ARC_REG_TLBPD0		0x405

#define ARC_REG_TLBPD1		0x406

#define ARC_REG_TLBINDEX	0x407

#define ARC_REG_TLBCOMMAND	0x408

#define ARC_REG_PID		0x409

#define ARC_REG_SCRATCH_DATA0	0x418



/* Bits in MMU PID register */

#define MMU_ENABLE		(1 << 31)	/* Enable MMU for process */



/* Error code if probe fails */

#define TLB_LKUP_ERR		0x80000000



/* TLB Commands */

#define TLBWrite    0x1

#define TLBRead     0x2

#define TLBGetIndex 0x3

#define TLBProbe    0x4



#if (CONFIG_ARC_MMU_VER >= 2)

#define TLBWriteNI  0x5		/* write JTLB without inv uTLBs */

#define TLBIVUTLB   0x6		/* explicitly inv uTLBs */

#endif



#ifndef __ASSEMBLY__



typedef struct {
@@ -26,6 +52,16 @@ typedef struct { 
#endif

} mm_context_t;



#ifdef CONFIG_ARC_DBG_TLB_PARANOIA

void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);

#else

#define tlb_paranoid_check(a, b)

#endif



void arc_mmu_init(void);

extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);

void __init read_decode_mmu_bcr(void);



#endif	/* !__ASSEMBLY__ */



#endif

arch/arc/include/asm/pgtable.h

+6 −0
Original line number Diff line number Diff line
@@ -135,6 +135,12 @@ 
/* ioremap */

#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)



/* Masks for actual TLB "PD"s */

#define PTE_BITS_IN_PD0	(_PAGE_GLOBAL | _PAGE_PRESENT)

#define PTE_BITS_IN_PD1	(PAGE_MASK | _PAGE_CACHEABLE | \

			 _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \

			 _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)



/**************************************************************************

 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

 *