Loading arch/arc/kernel/irq.c +3 −9 Original line number Diff line number Diff line Loading @@ -38,15 +38,9 @@ void __cpuinit arc_init_IRQ(void) write_aux_reg(AUX_IENABLE, 0); /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ #ifdef CONFIG_ARC_IRQ3_LV2 level_mask |= (1 << 3); #endif #ifdef CONFIG_ARC_IRQ5_LV2 level_mask |= (1 << 5); #endif #ifdef CONFIG_ARC_IRQ6_LV2 level_mask |= (1 << 6); #endif level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; if (level_mask) { pr_info("Level-2 interrupts bitset %x\n", level_mask); Loading Loading
arch/arc/kernel/irq.c +3 −9 Original line number Diff line number Diff line Loading @@ -38,15 +38,9 @@ void __cpuinit arc_init_IRQ(void) write_aux_reg(AUX_IENABLE, 0); /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ #ifdef CONFIG_ARC_IRQ3_LV2 level_mask |= (1 << 3); #endif #ifdef CONFIG_ARC_IRQ5_LV2 level_mask |= (1 << 5); #endif #ifdef CONFIG_ARC_IRQ6_LV2 level_mask |= (1 << 6); #endif level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; if (level_mask) { pr_info("Level-2 interrupts bitset %x\n", level_mask); Loading