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Unverified Commit d1f2564a authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Paul Burton
Browse files

MIPS: ath25: use generic dma noncoherent ops 



Provide phys_to_dma/dma_to_phys helpers only if PCI support is
enabled, everything else is generic.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Patchwork: https://patchwork.linux-mips.org/patch/19547/


Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org
parent 03df8229

arch/mips/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -182,7 +182,6 @@ config ATH25 
	select DMA_NONCOHERENT

	select IRQ_MIPS_CPU

	select IRQ_DOMAIN

	select MIPS_DMA_DEFAULT

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/ath25/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ config SOC_AR2315 
config PCI_AR2315

	bool "Atheros AR2315 PCI controller support"

	depends on SOC_AR2315

	select ARCH_HAS_PHYS_TO_DMA

	select HW_HAS_PCI

	select PCI

	default y

arch/mips/include/asm/mach-ath25/dma-coherence.h

deleted100644 → 0
+0 −71
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>

 * Copyright (C) 2007  Felix Fietkau <nbd@openwrt.org>

 *

 */

#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H

#define __ASM_MACH_ATH25_DMA_COHERENCE_H



#include <linux/device.h>



/*

 * We need some arbitrary non-zero value to be programmed to the BAR1 register

 * of PCI host controller to enable DMA. The same value should be used as the

 * offset to calculate the physical address of DMA buffer for PCI devices.

 */

#define AR2315_PCI_HOST_SDRAM_BASEADDR	0x20000000



static inline dma_addr_t ath25_dev_offset(struct device *dev)

{

#ifdef CONFIG_PCI

	extern struct bus_type pci_bus_type;



	if (dev && dev->bus == &pci_bus_type)

		return AR2315_PCI_HOST_SDRAM_BASEADDR;

#endif

	return 0;

}



static inline dma_addr_t

plat_map_dma_mem(struct device *dev, void *addr, size_t size)

{

	return virt_to_phys(addr) + ath25_dev_offset(dev);

}



static inline dma_addr_t

plat_map_dma_mem_page(struct device *dev, struct page *page)

{

	return page_to_phys(page) + ath25_dev_offset(dev);

}



static inline unsigned long

plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)

{

	return dma_addr - ath25_dev_offset(dev);

}



static inline void

plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,

		   enum dma_data_direction direction)

{

}



static inline int plat_dma_supported(struct device *dev, u64 mask)

{

	return 1;

}



static inline int plat_device_is_coherent(struct device *dev)

{

	return 0;

}



static inline void plat_post_dma_flush(struct device *dev)

{

}



#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */

arch/mips/pci/pci-ar2315.c

+24 −0
Original line number Diff line number Diff line
@@ -149,6 +149,13 @@ 
#define AR2315_PCI_HOST_SLOT	3

#define AR2315_PCI_HOST_DEVID	((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)



/*

 * We need some arbitrary non-zero value to be programmed to the BAR1 register

 * of PCI host controller to enable DMA. The same value should be used as the

 * offset to calculate the physical address of DMA buffer for PCI devices.

 */

#define AR2315_PCI_HOST_SDRAM_BASEADDR	0x20000000



/* ??? access BAR */

#define AR2315_PCI_HOST_MBAR0		0x10000000

/* RAM access BAR */
@@ -167,6 +174,23 @@ struct ar2315_pci_ctrl { 
	struct resource io_res;

};



static inline dma_addr_t ar2315_dev_offset(struct device *dev)

{

	if (dev && dev_is_pci(dev))

		return AR2315_PCI_HOST_SDRAM_BASEADDR;

	return 0;

}



dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)

{

	return paddr + ar2315_dev_offset(dev);

}



phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)

{

	return dma_addr - ar2315_dev_offset(dev);

}



static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)

{

	struct pci_controller *hose = bus->sysdata;