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Unverified Commit 03df8229 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Paul Burton
Browse files

MIPS: IP32: use generic dma noncoherent ops 



Provide phys_to_dma/dma_to_phys helpers, everything else is generic.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Patchwork: https://patchwork.linux-mips.org/patch/19546/


Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org
parent e905086e

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -726,6 +726,7 @@ config SGI_IP28 


config SGI_IP32

	bool "SGI IP32 (O2)"

	select ARCH_HAS_PHYS_TO_DMA

	select FW_ARC

	select FW_ARC32

	select BOOT_ELF32
@@ -734,7 +735,6 @@ config SGI_IP32 
	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_MIPS_CPU

	select MIPS_DMA_DEFAULT

	select R5000_CPU_SCACHE

	select RM7000_CPU_SCACHE

	select SYS_HAS_CPU_R5000

arch/mips/include/asm/mach-ip32/dma-coherence.h

deleted100644 → 0
+0 −92
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>

 *

 */

#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H

#define __ASM_MACH_IP32_DMA_COHERENCE_H



#include <asm/ip32/crime.h>



struct device;



/*

 * Few notes.

 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M

 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for

 *    native-endian)

 * 3. All other devices see memory as one big chunk at 0x40000000

 * 4. Non-PCI devices will pass NULL as struct device*

 *

 * Thus we translate differently, depending on device.

 */



#define RAM_OFFSET_MASK 0x3fffffffUL



static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,

	size_t size)

{

	dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;



	if (dev == NULL)

		pa += CRIME_HI_MEM_BASE;



	return pa;

}



static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,

	struct page *page)

{

	dma_addr_t pa;



	pa = page_to_phys(page) & RAM_OFFSET_MASK;



	if (dev == NULL)

		pa += CRIME_HI_MEM_BASE;



	return pa;

}



/* This is almost certainly wrong but it's what dma-ip32.c used to use	*/

static inline unsigned long plat_dma_addr_to_phys(struct device *dev,

	dma_addr_t dma_addr)

{

	unsigned long addr = dma_addr & RAM_OFFSET_MASK;



	if (dma_addr >= 256*1024*1024)

		addr += CRIME_HI_MEM_BASE;



	return addr;

}



static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,

	size_t size, enum dma_data_direction direction)

{

}



static inline int plat_dma_supported(struct device *dev, u64 mask)

{

	/*

	 * we fall back to GFP_DMA when the mask isn't all 1s,

	 * so we can't guarantee allocations that must be

	 * within a tighter range than GFP_DMA..

	 */

	if (mask < DMA_BIT_MASK(24))

		return 0;



	return 1;

}



static inline void plat_post_dma_flush(struct device *dev)

{

}



static inline int plat_device_is_coherent(struct device *dev)

{

	return 0;		/* IP32 is non-coherent */

}



#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */

arch/mips/sgi-ip32/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -4,4 +4,4 @@ 
#



obj-y	+= ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \

	   crime.o ip32-memory.o
 
	   crime.o ip32-memory.o ip32-dma.o

arch/mips/sgi-ip32/ip32-dma.c

0 → 100644
+37 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>

 */

#include <linux/dma-direct.h>

#include <asm/ip32/crime.h>



/*

 * Few notes.

 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M

 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for

 *    native-endian)

 * 3. All other devices see memory as one big chunk at 0x40000000

 * 4. Non-PCI devices will pass NULL as struct device*

 *

 * Thus we translate differently, depending on device.

 */



#define RAM_OFFSET_MASK 0x3fffffffUL



dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)

{

	dma_addr_t dma_addr = paddr & RAM_OFFSET_MASK;



	if (!dev)

		dma_addr += CRIME_HI_MEM_BASE;

	return dma_addr;

}



phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)

{

	phys_addr_t paddr = dma_addr & RAM_OFFSET_MASK;



	if (dma_addr >= 256*1024*1024)

		paddr += CRIME_HI_MEM_BASE;

	return paddr;

}