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Commit ce914e6b authored by Rob Herring's avatar Rob Herring Committed by Brian Norris
Browse files

mtd: nand: pxa3xx: fix build on ARM64 



In preparation to enable ARCH_MMP on ARM64, a couple of fixes are needed
to build the pxa3xx_nand driver:

Legacy DMA will only used on ARM, so also make it condtional on
CONFIG_ARM.
__raw_{read,write}sl are not available on ARM64 or generically, so use
the readsl/writesl variants instead. Somewhat inconsistently,
{read,write}sl are inherently non-swapping with the generic version
using __raw_{read,write}l.

Signed-off-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
[Brian: added one more __raw_readsl -> readsl]
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent afca11ec

drivers/mtd/nand/pxa3xx_nand.c

+10 −11
Original line number Original line Diff line number Diff line
@@ -29,7 +29,7 @@ 
#include <linux/of_device.h>

#include <linux/of_device.h>

#include <linux/of_mtd.h>

#include <linux/of_mtd.h>





#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)

#if defined(CONFIG_ARM) && (defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP))

#define ARCH_HAS_DMA

#define ARCH_HAS_DMA

#endif

#endif
@@ -496,7 +496,7 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) 
		 * the polling on the last read.

		 * the polling on the last read.

		 */

		 */

		while (len > 8) {

		while (len > 8) {

			__raw_readsl(info->mmio_base + NDDB, data, 8);

			readsl(info->mmio_base + NDDB, data, 8);





			ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,

			ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,

							 val & NDSR_RDDREQ, 1000, 5000);

							 val & NDSR_RDDREQ, 1000, 5000);
@@ -511,7 +511,7 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) 
		}

		}

	}

	}





	__raw_readsl(info->mmio_base + NDDB, data, len);

	readsl(info->mmio_base + NDDB, data, len);

}

}





static void handle_data_pio(struct pxa3xx_nand_info *info)

static void handle_data_pio(struct pxa3xx_nand_info *info)
@@ -520,12 +520,12 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) 




	switch (info->state) {

	switch (info->state) {

	case STATE_PIO_WRITING:

	case STATE_PIO_WRITING:

		__raw_writesl(info->mmio_base + NDDB,

		writesl(info->mmio_base + NDDB,

			info->data_buff + info->data_buff_pos,

			info->data_buff + info->data_buff_pos,

			DIV_ROUND_UP(do_bytes, 4));

			DIV_ROUND_UP(do_bytes, 4));





		if (info->oob_size > 0)

		if (info->oob_size > 0)

			__raw_writesl(info->mmio_base + NDDB,

			writesl(info->mmio_base + NDDB,

				info->oob_buff + info->oob_buff_pos,

				info->oob_buff + info->oob_buff_pos,

				DIV_ROUND_UP(info->oob_size, 4));

				DIV_ROUND_UP(info->oob_size, 4));

		break;

		break;
@@ -1628,8 +1628,7 @@ static int alloc_nand_resource(struct platform_device *pdev) 
	info->pdev = pdev;

	info->pdev = pdev;

	info->variant = pxa3xx_nand_get_variant(pdev);

	info->variant = pxa3xx_nand_get_variant(pdev);

	for (cs = 0; cs < pdata->num_cs; cs++) {

	for (cs = 0; cs < pdata->num_cs; cs++) {

		mtd = (struct mtd_info *)((unsigned int)&info[1] +

		mtd = (void *)&info[1] + (sizeof(*mtd) + sizeof(*host)) * cs;

		      (sizeof(*mtd) + sizeof(*host)) * cs);

		chip = (struct nand_chip *)(&mtd[1]);

		chip = (struct nand_chip *)(&mtd[1]);

		host = (struct pxa3xx_nand_host *)chip;

		host = (struct pxa3xx_nand_host *)chip;

		info->host[cs] = host;

		info->host[cs] = host;