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Commit c8d9fdbe authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node 



Add the missing L2 cache-controller node, and link the CPU nodes to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 374e7007

arch/arm/boot/dts/sh73a0.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
			reg = <0>;

			clock-frequency = <1196000000>;

			power-domains = <&pd_a2sl>;

			next-level-cache = <&L2>;

		};

		cpu@1 {

			device_type = "cpu";
@@ -35,6 +36,7 @@ 
			reg = <1>;

			clock-frequency = <1196000000>;

			power-domains = <&pd_a2sl>;

			next-level-cache = <&L2>;

		};

	};
@@ -53,6 +55,18 @@ 
		      <0xf0000100 0x100>;

	};



	L2: cache-controller {

		compatible = "arm,pl310-cache";

		reg = <0xf0100000 0x1000>;

		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&pd_a3sm>;

		arm,data-latency = <3 3 3>;

		arm,tag-latency = <2 2 2>;

		arm,shared-override;

		cache-unified;

		cache-level = <2>;

	};



	sbsc2: memory-controller@fb400000 {

		compatible = "renesas,sbsc-sh73a0";

		reg = <0xfb400000 0x400>;