Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 374e7007 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node 



Add the missing L2 cache-controller node, and link the CPU node to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c175e7ab

arch/arm/boot/dts/r8a7740.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
			reg = <0x0>;

			clock-frequency = <800000000>;

			power-domains = <&pd_a3sm>;

			next-level-cache = <&L2>;

		};

	};
@@ -37,6 +38,18 @@ 
		      <0xc2000000 0x1000>;

	};



	L2: cache-controller {

		compatible = "arm,pl310-cache";

		reg = <0xf0100000 0x1000>;

		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&pd_a3sm>;

		arm,data-latency = <3 3 3>;

		arm,tag-latency = <2 2 2>;

		arm,shared-override;

		cache-unified;

		cache-level = <2>;

	};



	dbsc3: memory-controller@fe400000 {

		compatible = "renesas,dbsc3-r8a7740";

		reg = <0xfe400000 0x400>;