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Commit bf933dbb authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-designware', 'pci/host-designware-common',... 

Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and 'pci/host-xgene' into next

* pci/host-designware:
  PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM
  PCI: designware: Consolidate outbound iATU programming functions
  PCI: designware: Add support for x8 links

* pci/host-designware-common:
  PCI: designware: Wait for link to come up with consistent style
  PCI: layerscape: Factor out ls_pcie_establish_link()
  PCI: layerscape: Use dw_pcie_link_up() consistently
  PCI: dra7xx: Use dw_pcie_link_up() consistently
  PCI: imx6: Rename imx6_pcie_start_link() to imx6_pcie_establish_link()

* pci/host-generic:
  of/pci: Fix pci_address_to_pio() conversion of CPU address to I/O port

* pci/host-imx6:
  PCI: imx6: Add #define PCIE_RC_LCSR
  PCI: imx6: Use "u32", not "uint32_t"
  PCI: imx6: Add speed change timeout message

* pci/host-iproc:
  PCI: iproc: Free resource list after registration
  PCI: iproc: Directly add PCI resources
  PCI: iproc: Add BCMA PCIe driver
  PCI: iproc: Allow override of device tree IRQ mapping function

* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe MSI nodes
  PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver
parents 0ff9b9ba 2d91b491 6cbb247e 5dbb4c61 2393f79c ef07991a e1e6e5c4

Documentation/devicetree/bindings/pci/xgene-pci-msi.txt

0 → 100644
+68 −0
Original line number Diff line number Diff line 
* AppliedMicro X-Gene v1 PCIe MSI controller



Required properties:



- compatible: should be "apm,xgene1-msi" to identify

	      X-Gene v1 PCIe MSI controller block.

- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node

- reg: physical base address (0x79000000) and length (0x900000) for controller

       registers. These registers include the MSI termination address and data

       registers as well as the MSI interrupt status registers.

- reg-names: not required

- interrupts: A list of 16 interrupt outputs of the controller, starting from

	      interrupt number 0x10 to 0x1f.

- interrupt-names: not required



Each PCIe node needs to have property msi-parent that points to msi controller node



Examples:



SoC DTSI:



	+ MSI node:

	msi@79000000 {

		compatible = "apm,xgene1-msi";

		msi-controller;

		reg = <0x00 0x79000000 0x0 0x900000>;

		interrupts = 	<0x0 0x10 0x4>

				<0x0 0x11 0x4>

				<0x0 0x12 0x4>

				<0x0 0x13 0x4>

				<0x0 0x14 0x4>

				<0x0 0x15 0x4>

				<0x0 0x16 0x4>

				<0x0 0x17 0x4>

				<0x0 0x18 0x4>

				<0x0 0x19 0x4>

				<0x0 0x1a 0x4>

				<0x0 0x1b 0x4>

				<0x0 0x1c 0x4>

				<0x0 0x1d 0x4>

				<0x0 0x1e 0x4>

				<0x0 0x1f 0x4>;

	};



	+ PCIe controller node with msi-parent property pointing to MSI node:

	pcie0: pcie@1f2b0000 {

		status = "disabled";

		device_type = "pci";

		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */

			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */

		reg-names = "csr", "cfg";

		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */

			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */

		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

		interrupt-map-mask = <0x0 0x0 0x0 0x7>;

		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1

				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1

				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1

				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;

		dma-coherent;

		clocks = <&pcie0clk 0>;

		msi-parent= <&msi>;

	};

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -7564,6 +7564,14 @@ L: linux-pci@vger.kernel.org 
S:	Orphan

F:	drivers/pci/host/*spear*



PCI MSI DRIVER FOR APPLIEDMICRO XGENE

M:	Duc Dang <dhdang@apm.com>

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/xgene-pci-msi.txt

F:	drivers/pci/host/pci-xgene-msi.c



PCMCIA SUBSYSTEM

P:	Linux PCMCIA Team

L:	linux-pcmcia@lists.infradead.org

arch/arm64/boot/dts/apm/apm-storm.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -374,6 +374,28 @@ 
			};

		};



		msi: msi@79000000 {

			compatible = "apm,xgene1-msi";

			msi-controller;

			reg = <0x00 0x79000000 0x0 0x900000>;

			interrupts = <  0x0 0x10 0x4

					0x0 0x11 0x4

					0x0 0x12 0x4

					0x0 0x13 0x4

					0x0 0x14 0x4

					0x0 0x15 0x4

					0x0 0x16 0x4

					0x0 0x17 0x4

					0x0 0x18 0x4

					0x0 0x19 0x4

					0x0 0x1a 0x4

					0x0 0x1b 0x4

					0x0 0x1c 0x4

					0x0 0x1d 0x4

					0x0 0x1e 0x4

					0x0 0x1f 0x4>;

		};



		pcie0: pcie@1f2b0000 {

			status = "disabled";

			device_type = "pci";
@@ -395,6 +417,7 @@ 
					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;

			dma-coherent;

			clocks = <&pcie0clk 0>;

			msi-parent = <&msi>;

		};



		pcie1: pcie@1f2c0000 {
@@ -418,6 +441,7 @@ 
					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;

			dma-coherent;

			clocks = <&pcie1clk 0>;

			msi-parent = <&msi>;

		};



		pcie2: pcie@1f2d0000 {
@@ -441,6 +465,7 @@ 
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;

			dma-coherent;

			clocks = <&pcie2clk 0>;

			msi-parent = <&msi>;

		};



		pcie3: pcie@1f500000 {
@@ -464,6 +489,7 @@ 
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;

			dma-coherent;

			clocks = <&pcie3clk 0>;

			msi-parent = <&msi>;

		};



		pcie4: pcie@1f510000 {
@@ -487,6 +513,7 @@ 
					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;

			dma-coherent;

			clocks = <&pcie4clk 0>;

			msi-parent = <&msi>;

		};



		serial0: serial@1c020000 {

drivers/of/address.c

+1 −1
Original line number Diff line number Diff line
@@ -765,7 +765,7 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address) 
	spin_lock(&io_range_lock);

	list_for_each_entry(res, &io_range_list, list) {

		if (address >= res->start && address < res->start + res->size) {

			addr = res->start - address + offset;

			addr = address - res->start + offset;

			break;

		}

		offset += res->size;

drivers/pci/host/Kconfig

+20 −0
Original line number Diff line number Diff line
@@ -89,11 +89,20 @@ config PCI_XGENE 
	depends on ARCH_XGENE

	depends on OF

	select PCIEPORTBUS

	select PCI_MSI_IRQ_DOMAIN if PCI_MSI

	help

	  Say Y here if you want internal PCI support on APM X-Gene SoC.

	  There are 5 internal PCIe ports available. Each port is GEN3 capable

	  and have varied lanes from x1 to x8.



config PCI_XGENE_MSI

	bool "X-Gene v1 PCIe MSI feature"

	depends on PCI_XGENE && PCI_MSI

	default y

	help

	  Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.

	  This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC.



config PCI_LAYERSCAPE

	bool "Freescale Layerscape PCIe controller"

	depends on OF && ARM
@@ -125,4 +134,15 @@ config PCIE_IPROC_PLATFORM 
	  Say Y here if you want to use the Broadcom iProc PCIe controller

	  through the generic platform bus interface



config PCIE_IPROC_BCMA

	bool "Broadcom iProc PCIe BCMA bus driver"

	depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)

	select PCIE_IPROC

	select BCMA

	select PCI_DOMAINS

	default ARCH_BCM_5301X

	help

	  Say Y here if you want to use the Broadcom iProc PCIe controller

	  through the BCMA bus interface



endmenu