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Commit b55b9e27 authored by Markos Chandras's avatar Markos Chandras
Browse files

MIPS: asm: mipsregs: Add support for the LLADDR register 



If Config5/LLB is set in the core, then software can write the LLB
bit in the LLADDR register.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 5aed9da1

arch/mips/include/asm/mipsregs.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -1128,6 +1128,8 @@ do { \ 
#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)

#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)

#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)

#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)





#define read_c0_lladdr()	__read_ulong_c0_register($17, 0)

#define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)

#define read_c0_maar()		__read_ulong_c0_register($17, 1)

#define read_c0_maar()		__read_ulong_c0_register($17, 1)

#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)

#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)

#define read_c0_maari()		__read_32bit_c0_register($17, 2)

#define read_c0_maari()		__read_32bit_c0_register($17, 2)