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Commit 5aed9da1 authored by Markos Chandras's avatar Markos Chandras
Browse files

MIPS: Add LLB bit and related feature for the Config 5 CP0 register 



The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:

0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:

- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]

This will be used later on to emulate R2 LL/SC instructions.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 28d6f93d

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -38,6 +38,9 @@ 
#ifndef cpu_has_maar

#define cpu_has_maar		(cpu_data[0].options & MIPS_CPU_MAAR)

#endif

#ifndef cpu_has_rw_llb

#define cpu_has_rw_llb		(cpu_data[0].options & MIPS_CPU_RW_LLB)

#endif



/*

 * For the moment we don't consider R6000 and R8000 so we can assume that

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -376,6 +376,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */

#define MIPS_CPU_MAAR		0x400000000ull /* MAAR(I) registers are present */

#define MIPS_CPU_FRE		0x800000000ull /* FRE & UFE bits implemented */

#define MIPS_CPU_RW_LLB		0x1000000000ull /* LLADDR/LLB writes are allowed */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+1 −0
Original line number Diff line number Diff line
@@ -653,6 +653,7 @@ 
#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)

#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)

#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)

#define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)

#define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)

#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)

#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -514,6 +514,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c) 
		c->options |= MIPS_CPU_EVA;

	if (config5 & MIPS_CONF5_MRP)

		c->options |= MIPS_CPU_MAAR;

	if (config5 & MIPS_CONF5_LLB)

		c->options |= MIPS_CPU_RW_LLB;



	return config5 & MIPS_CONF_M;

}