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Commit a7546159 authored by Nick Hoath's avatar Nick Hoath Committed by Daniel Vetter
Browse files

drm/i915/bxt: Clean up bxt_init_clock_gating 



Add stepping check for A0 workarounds, and remove the associated
FIXME tags.
Split out unrelated WAs for later condition checking.

v2: Fixed format (PeterL)
v3: Corrected stepping check for WaDisableSDEUnitClockGating
    - Ignoring comment, following hardware spec instead. (ChrisH)
    Added description for TILECTL setting (JonB)

Cc: Peter Lawthers <peter.lawthers@intel.com>
Cc: Chris Harris <chris.harris@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 614f4ad7

drivers/gpu/drm/i915/intel_pm.c

+11 −5
Original line number Diff line number Diff line
@@ -116,19 +116,25 @@ static void bxt_init_clock_gating(struct drm_device *dev) 


	gen9_init_clock_gating(dev);



	/* WaDisableSDEUnitClockGating:bxt */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/*

	 * FIXME:

	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.

	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.

	 */

	 /* WaDisableSDEUnitClockGating:bxt */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |

		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);



	/* FIXME: apply on A0 only */

	if (INTEL_REVID(dev) == BXT_REVID_A0) {

		/*

		 * Hardware specification requires this bit to be

		 * set to 1 for A0

		 */

		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);

	}

}



static void i915_pineview_get_mem_freq(struct drm_device *dev)

{