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Commit 614f4ad7 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Fix cmdparser STORE/LOAD command descriptors 

Fixes regression from
commit f1afe24f
Author: Arun Siluvery <arun.siluvery@linux.intel.com>
Date:   Tue Aug 4 16:22:20 2015 +0100

    drm/i915: Change SRM, LRM instructions to use correct length

which forgot to account for the length bias when declaring the fixed
length.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91844


Reported-by: default avatarAndreas Reis <andreas.reis@gmail.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 333b8ca8

drivers/gpu/drm/i915/i915_cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = { 
	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),

	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,

	      .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),

	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  1,     W | B,

	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,

	      .reg = { .offset = 1, .mask = 0x007FFFFC },

	      .bits = {{

			.offset = 0,

			.mask = MI_GLOBAL_GTT,

			.expected = 0,

	      }},						       ),

	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  1,     W | B,

	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,

	      .reg = { .offset = 1, .mask = 0x007FFFFC },

	      .bits = {{

			.offset = 0,