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Commit a2d30b9c authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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ARM: dts: r8a7792: add VIN support 



Define the generic R8A7792 parts of the VIN[0-5] device nodes.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 62855bcf

arch/arm/boot/dts/r8a7792.dtsi

+66 −0
Original line number Diff line number Diff line
@@ -25,6 +25,12 @@ 
		i2c3 = &i2c3;

		i2c4 = &i2c4;

		i2c5 = &i2c5;

		vin0 = &vin0;

		vin1 = &vin1;

		vin2 = &vin2;

		vin3 = &vin3;

		vin4 = &vin4;

		vin5 = &vin5;

};



	cpus {
@@ -574,6 +580,66 @@ 
			status = "disabled";

		};



		vin0: video@e6ef0000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef0000 0 0x1000>;

			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN0>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		vin1: video@e6ef1000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef1000 0 0x1000>;

			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN1>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		vin2: video@e6ef2000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef2000 0 0x1000>;

			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN2>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		vin3: video@e6ef3000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef3000 0 0x1000>;

			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN3>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		vin4: video@e6ef4000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef4000 0 0x1000>;

			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN4>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		vin5: video@e6ef5000 {

			compatible = "renesas,vin-r8a7792",

				     "renesas,rcar-gen2-vin";

			reg = <0 0xe6ef5000 0 0x1000>;

			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R8A7792_CLK_VIN5>;

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@e6150000 {

			compatible = "renesas,r8a7792-cpg-clocks",