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Commit a26be149 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:
 "This time with:

   - Generic page-table framework for ARM IOMMUs using the LPAE
     page-table format, ARM-SMMU and Renesas IPMMU make use of it
     already.

   - Break out the IO virtual address allocator from the Intel IOMMU so
     that it can be used by other DMA-API implementations too.  The
     first user will be the ARM64 common DMA-API implementation for
     IOMMUs

   - Device tree support for Renesas IPMMU

   - Various fixes and cleanups all over the place"

* tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (36 commits)
  iommu/amd: Convert non-returned local variable to boolean when relevant
  iommu: Update my email address
  iommu/amd: Use wait_event in put_pasid_state_wait
  iommu/amd: Fix amd_iommu_free_device()
  iommu/arm-smmu: Avoid build warning
  iommu/fsl: Various cleanups
  iommu/fsl: Use %pa to print phys_addr_t
  iommu/omap: Print phys_addr_t using %pa
  iommu: Make more drivers depend on COMPILE_TEST
  iommu/ipmmu-vmsa: Fix IOMMU lookup when multiple IOMMUs are registered
  iommu: Disable on !MMU builds
  iommu/fsl: Remove unused fsl_of_pamu_ids[]
  iommu/fsl: Fix section mismatch
  iommu/ipmmu-vmsa: Use the ARM LPAE page table allocator
  iommu: Fix trace_map() to report original iova and original size
  iommu/arm-smmu: add support for iova_to_phys through ATS1PR
  iopoll: Introduce memory-mapped IO polling macros
  iommu/arm-smmu: don't touch the secure STLBIALL register
  iommu/arm-smmu: make use of generic LPAE allocator
  iommu: io-pgtable-arm: add non-secure quirk
  ...
parents cdd30545 a20cc76b

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt

0 → 100644
+41 −0
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* Renesas VMSA-Compatible IOMMU



The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.

It provides address translation for bus masters outside of the CPU, each

connected to the IPMMU through a port called micro-TLB.





Required Properties:



  - compatible: Must contain "renesas,ipmmu-vmsa".

  - reg: Base address and size of the IPMMU registers.

  - interrupts: Specifiers for the MMU fault interrupts. For instances that

    support secure mode two interrupts must be specified, for non-secure and

    secure mode, in that order. For instances that don't support secure mode a

    single interrupt must be specified.



  - #iommu-cells: Must be 1.



Each bus master connected to an IPMMU must reference the IPMMU in its device

node with the following property:



  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle

    to the IPMMU and the second cell the number of the micro-TLB that the

    device is connected to.





Example: R8A7791 IPMMU-MX and VSP1-D0 bus master



	ipmmu_mx: mmu@fe951000 {

		compatible = "renasas,ipmmu-vmsa";

		reg = <0 0xfe951000 0 0x1000>;

		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,

			     <0 221 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

	};



	vsp1@fe928000 {

		...

		iommus = <&ipmmu_mx 13>;

		...

	};

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1606,6 +1606,7 @@ M: Will Deacon <will.deacon@arm.com> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/iommu/arm-smmu.c

F:	drivers/iommu/io-pgtable-arm.c



ARM64 PORT (AARCH64 ARCHITECTURE)

M:	Catalin Marinas <catalin.marinas@arm.com>

arch/arm64/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -350,7 +350,6 @@ config ARM64_VA_BITS_42 


config ARM64_VA_BITS_48

	bool "48-bit"

	depends on !ARM_SMMU



endchoice

drivers/iommu/Kconfig

+43 −8
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ config IOMMU_API 


menuconfig IOMMU_SUPPORT

	bool "IOMMU Hardware Support"

	depends on MMU

	default y

	---help---

	  Say Y here if you want to compile device drivers for IO Memory
@@ -13,13 +14,43 @@ menuconfig IOMMU_SUPPORT 


if IOMMU_SUPPORT



menu "Generic IOMMU Pagetable Support"



# Selected by the actual pagetable implementations

config IOMMU_IO_PGTABLE

	bool



config IOMMU_IO_PGTABLE_LPAE

	bool "ARMv7/v8 Long Descriptor Format"

	select IOMMU_IO_PGTABLE

	help

	  Enable support for the ARM long descriptor pagetable format.

	  This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page

	  sizes at both stage-1 and stage-2, as well as address spaces

	  up to 48-bits in size.



config IOMMU_IO_PGTABLE_LPAE_SELFTEST

	bool "LPAE selftests"

	depends on IOMMU_IO_PGTABLE_LPAE

	help

	  Enable self-tests for LPAE page table allocator. This performs

	  a series of page-table consistency checks during boot.



	  If unsure, say N here.



endmenu



config IOMMU_IOVA

	bool



config OF_IOMMU

       def_bool y

       depends on OF && IOMMU_API



config FSL_PAMU

	bool "Freescale IOMMU support"

	depends on PPC_E500MC

	depends on PPC32

	depends on PPC_E500MC || COMPILE_TEST

	select IOMMU_API

	select GENERIC_ALLOCATOR

	help
@@ -30,7 +61,8 @@ config FSL_PAMU 
# MSM IOMMU support

config MSM_IOMMU

	bool "MSM IOMMU Support"

	depends on ARCH_MSM8X60 || ARCH_MSM8960

	depends on ARM

	depends on ARCH_MSM8X60 || ARCH_MSM8960 || COMPILE_TEST

	select IOMMU_API

	help

	  Support for the IOMMUs found on certain Qualcomm SOCs.
@@ -91,6 +123,7 @@ config INTEL_IOMMU 
	bool "Support for Intel IOMMU using DMA Remapping Devices"

	depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC)

	select IOMMU_API

	select IOMMU_IOVA

	select DMAR_TABLE

	help

	  DMA remapping (DMAR) devices support enables independent address
@@ -140,7 +173,8 @@ config IRQ_REMAP 
# OMAP IOMMU support

config OMAP_IOMMU

	bool "OMAP IOMMU Support"

	depends on ARCH_OMAP2PLUS

	depends on ARM && MMU

	depends on ARCH_OMAP2PLUS || COMPILE_TEST

	select IOMMU_API



config OMAP_IOMMU_DEBUG
@@ -187,7 +221,7 @@ config TEGRA_IOMMU_SMMU 


config EXYNOS_IOMMU

	bool "Exynos IOMMU Support"

	depends on ARCH_EXYNOS && ARM

	depends on ARCH_EXYNOS && ARM && MMU

	select IOMMU_API

	select ARM_DMA_USE_IOMMU

	help
@@ -216,7 +250,7 @@ config SHMOBILE_IPMMU_TLB 
config SHMOBILE_IOMMU

	bool "IOMMU for Renesas IPMMU/IPMMUI"

	default n

	depends on ARM

	depends on ARM && MMU

	depends on ARCH_SHMOBILE || COMPILE_TEST

	select IOMMU_API

	select ARM_DMA_USE_IOMMU
@@ -287,6 +321,7 @@ config IPMMU_VMSA 
	depends on ARM_LPAE

	depends on ARCH_SHMOBILE || COMPILE_TEST

	select IOMMU_API

	select IOMMU_IO_PGTABLE_LPAE

	select ARM_DMA_USE_IOMMU

	help

	  Support for the Renesas VMSA-compatible IPMMU Renesas found in the
@@ -304,13 +339,13 @@ config SPAPR_TCE_IOMMU 


config ARM_SMMU

	bool "ARM Ltd. System MMU (SMMU) Support"

	depends on ARM64 || (ARM_LPAE && OF)

	depends on (ARM64 || ARM) && MMU

	select IOMMU_API

	select IOMMU_IO_PGTABLE_LPAE

	select ARM_DMA_USE_IOMMU if ARM

	help

	  Support for implementations of the ARM System MMU architecture

	  versions 1 and 2. The driver supports both v7l and v8l table

	  formats with 4k and 64k page sizes.

	  versions 1 and 2.



	  Say Y here if your SoC includes an IOMMU device implementing

	  the ARM SMMU architecture.

drivers/iommu/Makefile

+4 −1
Original line number Diff line number Diff line 
obj-$(CONFIG_IOMMU_API) += iommu.o

obj-$(CONFIG_IOMMU_API) += iommu-traces.o

obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o

obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o

obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o

obj-$(CONFIG_IOMMU_IOVA) += iova.o

obj-$(CONFIG_OF_IOMMU)	+= of_iommu.o

obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o

obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o

obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o

obj-$(CONFIG_DMAR_TABLE) += dmar.o

obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o

obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o

obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o

obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o

obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o