Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cdd30545 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull DeviceTree changes from Rob Herring:

 - DT unittests for I2C probing and overlays from Pantelis Antoniou

 - Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha

 - Add Tegra compatible strings missing for newer parts from Paul
   Walmsley

 - Various vendor prefix additions

* tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  of: Add vendor prefix for OmniVision Technologies
  of: Use ovti for Omnivision
  of: Add vendor prefix for Truly Semiconductors Limited
  of: Add vendor prefix for Himax Technologies Inc.
  of/fdt: fix sparse warning
  of: unitest: Add I2C overlay unit tests.
  Documentation: DT: document compatible string existence requirement
  Documentation: DT bindings: add nvidia, tegra132-denver compatible string
  Documentation: DT bindings: add more Tegra chip compatible strings
  of: EXPORT_SYMBOL_GPL of_property_read_u64_array
  of: Fix brace position for struct of_device_id definition
  of/unittest: Remove obsolete code
  dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt
  Add AD Holdings Plc. to vendor-prefixes.
  dt-bindings: Add Silicon Mitus vendor prefix
  Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol
  pinctrl: fix up device tree bindings
  DT: Vendors: Add Everspin
  doc: add bindings document for altera fpga manager
  drivers: of: Export of_reserved_mem_device_{init,release}
parents 42cf0f20 3c3c8e36

Documentation/devicetree/bindings/arm/cpus.txt

+1 −0
Original line number Diff line number Diff line
@@ -175,6 +175,7 @@ nodes to be present and contain the properties described below. 
			    "marvell,pj4a"

			    "marvell,pj4b"

			    "marvell,sheeva-v5"

			    "nvidia,tegra132-denver"

			    "qcom,krait"

			    "qcom,scorpion"

	- enable-method

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt

+4 −1
Original line number Diff line number Diff line 
NVIDIA Tegra AHB



Required properties:

- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"

- compatible : For Tegra20, must contain "nvidia,tegra20-ahb".  For

  Tegra30, must contain "nvidia,tegra30-ahb".  Otherwise, must contain

  '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,

  tegra132, or tegra210.

- reg : Should contain 1 register ranges(address and length)



Example:

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+5 −1
Original line number Diff line number Diff line
@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands. 


Required properties:

- name : Should be pmc

- compatible : Should contain "nvidia,tegra<chip>-pmc".

- compatible : For Tegra20, must contain "nvidia,tegra20-pmc".  For Tegra30,

  must contain "nvidia,tegra30-pmc".  For Tegra114, must contain

  "nvidia,tegra114-pmc".  For Tegra124, must contain "nvidia,tegra124-pmc".

  Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the

  above, where <chip> is tegra132.

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

Documentation/devicetree/bindings/ata/tegra-sata.txt

+3 −1
Original line number Diff line number Diff line 
Tegra124 SoC SATA AHCI controller



Required properties :

- compatible : "nvidia,tegra124-ahci".

- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,

  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>

  is tegra132.

- reg : Should contain 2 entries:

  - AHCI register set (SATA BAR5)

  - SATA register set

Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt

0 → 100644
+17 −0
Original line number Diff line number Diff line 
Altera SOCFPGA FPGA Manager



Required properties:

- compatible : should contain "altr,socfpga-fpga-mgr"

- reg        : base address and size for memory mapped io.

               - The first index is for FPGA manager register access.

               - The second index is for writing FPGA configuration data.

- interrupts : interrupt for the FPGA Manager device.



Example:



	hps_0_fpgamgr: fpgamgr@0xff706000 {

		compatible = "altr,socfpga-fpga-mgr";

		reg = <0xFF706000 0x1000

		       0xFFB90000 0x1000>;

		interrupts = <0 175 4>;

	};