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Commit a13edd0b authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
Browse files

drm/nouveau/secboot: share r361 BL structures and functions 



Share elements of r361 that will be reused in other ACRs.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 114223aa

drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c

+2 −39
Original line number Diff line number Diff line
@@ -20,50 +20,13 @@ 
 * DEALINGS IN THE SOFTWARE.

 */



#include "acr_r352.h"

#include "acr_r361.h"



#include <engine/falcon.h>

#include <core/msgqueue.h>

#include <subdev/pmu.h>

#include <engine/sec2.h>



/**

 * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor

 * @signature:		16B signature for secure code. 0s if no secure code

 * @ctx_dma:		DMA context to be used by BL while loading code/data

 * @code_dma_base:	256B-aligned Physical FB Address where code is located

 *			(falcon's $xcbase register)

 * @non_sec_code_off:	offset from code_dma_base where the non-secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @non_sec_code_size:	the size of the nonSecure code part.

 * @sec_code_off:	offset from code_dma_base where the secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @sec_code_size:	offset from code_dma_base where the secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @code_entry_point:	code entry point which will be invoked by BL after

 *                      code is loaded.

 * @data_dma_base:	256B aligned Physical FB Address where data is located.

 *			(falcon's $xdbase register)

 * @data_size:		size of data block. Should be multiple of 256B

 *

 * Structure used by the bootloader to load the rest of the code. This has

 * to be filled by host and copied into DMEM at offset provided in the

 * hsflcn_bl_desc.bl_desc_dmem_load_off.

 */

struct acr_r361_flcn_bl_desc {

	u32 reserved[4];

	u32 signature[4];

	u32 ctx_dma;

	struct flcn_u64 code_dma_base;

	u32 non_sec_code_off;

	u32 non_sec_code_size;

	u32 sec_code_off;

	u32 sec_code_size;

	u32 code_entry_point;

	struct flcn_u64 data_dma_base;

	u32 data_size;

};



static void

acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr,

			       const struct ls_ucode_img *img, u64 wpr_addr,
@@ -86,7 +49,7 @@ acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, 
	desc->data_size = pdesc->app_resident_data_size;

}



static void

void

acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,

			    u64 offset)

{

drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.h

0 → 100644
+72 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#ifndef __NVKM_SECBOOT_ACR_R361_H__

#define __NVKM_SECBOOT_ACR_R361_H__



#include "acr_r352.h"



/**

 * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor

 * @signature:		16B signature for secure code. 0s if no secure code

 * @ctx_dma:		DMA context to be used by BL while loading code/data

 * @code_dma_base:	256B-aligned Physical FB Address where code is located

 *			(falcon's $xcbase register)

 * @non_sec_code_off:	offset from code_dma_base where the non-secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @non_sec_code_size:	the size of the nonSecure code part.

 * @sec_code_off:	offset from code_dma_base where the secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @sec_code_size:	offset from code_dma_base where the secure code is

 *                      located. The offset must be multiple of 256 to help perf

 * @code_entry_point:	code entry point which will be invoked by BL after

 *                      code is loaded.

 * @data_dma_base:	256B aligned Physical FB Address where data is located.

 *			(falcon's $xdbase register)

 * @data_size:		size of data block. Should be multiple of 256B

 *

 * Structure used by the bootloader to load the rest of the code. This has

 * to be filled by host and copied into DMEM at offset provided in the

 * hsflcn_bl_desc.bl_desc_dmem_load_off.

 */

struct acr_r361_flcn_bl_desc {

	u32 reserved[4];

	u32 signature[4];

	u32 ctx_dma;

	struct flcn_u64 code_dma_base;

	u32 non_sec_code_off;

	u32 non_sec_code_size;

	u32 sec_code_off;

	u32 sec_code_size;

	u32 code_entry_point;

	struct flcn_u64 data_dma_base;

	u32 data_size;

};



void acr_r361_generate_hs_bl_desc(const struct hsf_load_header *, void *, u64);



extern const struct acr_r352_ls_func acr_r361_ls_fecs_func;

extern const struct acr_r352_ls_func acr_r361_ls_gpccs_func;

extern const struct acr_r352_ls_func acr_r361_ls_pmu_func;

extern const struct acr_r352_ls_func acr_r361_ls_sec2_func;



#endif