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Commit 114223aa authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
Browse files

drm/nouveau/secboot: add support for SEC LS firmware 



Support running a message queue firmware on SEC.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 48387f0c

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ enum nvkm_falcon_dmaidx { 
	FALCON_DMAIDX_PHYS_VID		= 2,

	FALCON_DMAIDX_PHYS_SYS_COH	= 3,

	FALCON_DMAIDX_PHYS_SYS_NCOH	= 4,

	FALCON_SEC2_DMAIDX_UCODE	= 6,

};



struct nvkm_falcon {

drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c

+42 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <engine/falcon.h>

#include <core/msgqueue.h>

#include <subdev/pmu.h>

#include <engine/sec2.h>



/**

 * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor
@@ -169,6 +170,46 @@ acr_r361_ls_pmu_func = { 
	.post_run = acr_ls_pmu_post_run,

};



static void

acr_r361_generate_sec2_bl_desc(const struct nvkm_acr *acr,

			       const struct ls_ucode_img *img, u64 wpr_addr,

			       void *_desc)

{

	const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;

	const struct nvkm_sec2 *sec = acr->subdev->device->sec2;

	struct acr_r361_pmu_bl_desc *desc = _desc;

	u64 base, addr_code, addr_data;

	u32 addr_args;



	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;

	/* For some reason we should not add app_resident_code_offset here */

	addr_code = base;

	addr_data = base + pdesc->app_resident_data_offset;

	addr_args = sec->falcon->data.limit;

	addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;



	desc->dma_idx = FALCON_SEC2_DMAIDX_UCODE;

	desc->code_dma_base = u64_to_flcn64(addr_code);

	desc->total_code_size = pdesc->app_size;

	desc->code_size_to_load = pdesc->app_resident_code_size;

	desc->code_entry_point = pdesc->app_imem_entry;

	desc->data_dma_base = u64_to_flcn64(addr_data);

	desc->data_size = pdesc->app_resident_data_size;

	desc->overlay_dma_base = u64_to_flcn64(addr_code);

	desc->argc = 1;

	/* args are stored at the beginning of EMEM */

	desc->argv = 0x01000000;

}



const struct acr_r352_ls_func

acr_r361_ls_sec2_func = {

	.load = acr_ls_ucode_load_sec2,

	.generate_bl_desc = acr_r361_generate_sec2_bl_desc,

	.bl_desc_size = sizeof(struct acr_r361_pmu_bl_desc),

	.post_run = acr_ls_sec2_post_run,

};





const struct acr_r352_func

acr_r361_func = {

	.fixup_hs_desc = acr_r352_fixup_hs_desc,
@@ -181,6 +222,7 @@ acr_r361_func = { 
		[NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func,

		[NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func,

		[NVKM_SECBOOT_FALCON_PMU] = &acr_r361_ls_pmu_func,

		[NVKM_SECBOOT_FALCON_SEC2] = &acr_r361_ls_sec2_func,

	},

};

drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h

+2 −0
Original line number Diff line number Diff line
@@ -151,5 +151,7 @@ int acr_ls_ucode_load_fecs(const struct nvkm_subdev *, struct ls_ucode_img *); 
int acr_ls_ucode_load_gpccs(const struct nvkm_subdev *, struct ls_ucode_img *);

int acr_ls_ucode_load_pmu(const struct nvkm_subdev *, struct ls_ucode_img *);

void acr_ls_pmu_post_run(const struct nvkm_acr *, const struct nvkm_secboot *);

int acr_ls_ucode_load_sec2(const struct nvkm_subdev *, struct ls_ucode_img *);

void acr_ls_sec2_post_run(const struct nvkm_acr *, const struct nvkm_secboot *);



#endif

drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c

+32 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <core/firmware.h>

#include <core/msgqueue.h>

#include <subdev/pmu.h>

#include <engine/sec2.h>



/**

 * acr_ls_ucode_load_msgqueue - load and prepare a ucode img for a msgqueue fw
@@ -115,3 +116,34 @@ acr_ls_pmu_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) 


	acr_ls_msgqueue_post_run(pmu->queue, pmu->falcon, addr_args);

}



int

acr_ls_ucode_load_sec2(const struct nvkm_subdev *subdev,

		       struct ls_ucode_img *img)

{

	struct nvkm_sec2 *sec = subdev->device->sec2;

	int ret;



	ret = acr_ls_ucode_load_msgqueue(subdev, "sec2", img);

	if (ret)

		return ret;



	/* Allocate the PMU queue corresponding to the FW version */

	ret = nvkm_msgqueue_new(img->ucode_desc.app_version, sec->falcon,

				&sec->queue);

	if (ret)

		return ret;



	return 0;

}



void

acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb)

{

	struct nvkm_device *device = sb->subdev.device;

	struct nvkm_sec2 *sec = device->sec2;

	/* on SEC arguments are always at the beginning of EMEM */

	u32 addr_args = 0x01000000;



	acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args);

}