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Commit 9afafdbf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel into drm-next 

Getting started with v4.15 features:

- Cannonlake workarounds (Rodrigo, Oscar)
- Infoframe refactoring and fixes to enable infoframes for DP (Ville)
- VBT definition updates (Jani)
- Sparse warning fixes (Ville, Chris)
- Crtc state usage fixes and cleanups (Ville)
- DP vswing, pre-emph and buffer translation refactoring and fixes (Rodrigo)
- Prevent IPS from interfering with CRC capture (Ville, Marta)
- Enable Mesa to advertise ARB_timer_query (Nanley)
- Refactor GT number into intel_device_info (Lionel)
- Avoid eDP DP AUX CH timeouts harder (Manasi)
- CDCLK check improvements (Ville)
- Restore GPU clock boost on missed pageflip vblanks (Chris)
- Fence register reservation API for vGPU (Changbin)
- First batch of CCS fixes (Ville)
- Finally, numerous GEM fixes, cleanups and improvements (Chris)

* tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel: (100 commits)
  drm/i915: Update DRIVER_DATE to 20170907
  drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)
  drm/i915: Lift has-pinned-pages assert to caller of ____i915_gem_object_get_pages
  drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
  drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register
  drm/i915: Move device_info.has_snoop into the static tables
  drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm
  drm/i915: Re-enable GTT following a device reset
  drm/i915/cnp: Wa 1181: Fix Backlight issue
  drm/i915: Annotate user relocs with __user
  drm/i915: Constify load detect mode
  drm/i915/perf: Remove __user from u64 in drm_i915_perf_oa_config
  drm/i915: Silence sparse by using gfp_t
  drm/i915: io unmap functions want __iomem
  drm/i915: Add __rcu to radix tree slot pointer
  drm/i915: Wake up the device for the fbdev setup
  drm/i915: Add interface to reserve fence registers for vGPU
  drm/i915: Use correct path to trace include
  drm/i915: Fix the missing PPAT cache attributes on CNL
  drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder
  ...
parents 29baa82a bb9d2d05

drivers/gpu/drm/i915/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -150,5 +150,3 @@ endif 
i915-y += intel_lpe_audio.o



obj-$(CONFIG_DRM_I915) += i915.o
 


CFLAGS_i915_trace_points.o := -I$(src)

drivers/gpu/drm/i915/gvt/aperture_gm.c

+11 −15
Original line number Diff line number Diff line
@@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) 
	_clear_vgpu_fence(vgpu);

	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = vgpu->fence.regs[i];

		list_add_tail(&reg->link,

			      &dev_priv->mm.fence_list);

		i915_unreserve_fence(reg);

		vgpu->fence.regs[i] = NULL;

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);
@@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) 
	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_fence_reg *reg;

	int i;

	struct list_head *pos, *q;



	intel_runtime_pm_get(dev_priv);



	/* Request fences from host */

	mutex_lock(&dev_priv->drm.struct_mutex);

	i = 0;

	list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {

		reg = list_entry(pos, struct drm_i915_fence_reg, link);

		if (reg->pin_count || reg->vma)

			continue;

		list_del(pos);



	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = i915_reserve_fence(dev_priv);

		if (IS_ERR(reg))

			goto out_free_fence;



		vgpu->fence.regs[i] = reg;

		if (++i == vgpu_fence_sz(vgpu))

			break;

	}

	if (i != vgpu_fence_sz(vgpu))

		goto out_free_fence;



	_clear_vgpu_fence(vgpu);
@@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) 
	intel_runtime_pm_put(dev_priv);

	return 0;

out_free_fence:

	gvt_vgpu_err("Failed to alloc fences\n");

	/* Return fences to host, if fail */

	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {

		reg = vgpu->fence.regs[i];

		if (!reg)

			continue;

		list_add_tail(&reg->link,

			      &dev_priv->mm.fence_list);

		i915_unreserve_fence(reg);

		vgpu->fence.regs[i] = NULL;

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

	intel_runtime_pm_put(dev_priv);

drivers/gpu/drm/i915/i915_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -239,7 +239,8 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv) 
				dev_priv->pch_type = PCH_KBP;

				DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");

				WARN_ON(!IS_SKYLAKE(dev_priv) &&

					!IS_KABYLAKE(dev_priv));

					!IS_KABYLAKE(dev_priv) &&

					!IS_COFFEELAKE(dev_priv));

			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_CNP;

				DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");

drivers/gpu/drm/i915/i915_drv.h

+42 −21
Original line number Diff line number Diff line
@@ -80,8 +80,8 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20170818"

#define DRIVER_TIMESTAMP	1503088845

#define DRIVER_DATE		"20170907"

#define DRIVER_TIMESTAMP	1504772900



/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and

 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -569,6 +569,24 @@ struct i915_hotplug { 
	     (__i)++) \

		for_each_if (plane_state)



#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \

	for ((__i) = 0; \

	     (__i) < (__state)->base.dev->mode_config.num_crtc && \

		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \

		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \

	     (__i)++) \

		for_each_if (crtc)





#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \

	for ((__i) = 0; \

	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \

		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \

		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \

		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \

	     (__i)++) \

		for_each_if (plane)



struct drm_i915_private;

struct i915_mm_struct;

struct i915_mmu_object;
@@ -841,6 +859,7 @@ struct intel_device_info { 
	u8 gen;

	u16 gen_mask;

	enum intel_platform platform;

	u8 gt; /* GT number, 0 if undefined */

	u8 ring_mask; /* Rings supported by the HW */

	u8 num_rings;

#define DEFINE_FLAG(name) u8 name:1
@@ -1106,6 +1125,7 @@ struct intel_fbc { 
		} fb;



		int cfb_size;

		unsigned int gen9_wa_cfb_stride;

	} params;



	struct intel_fbc_work {
@@ -1464,6 +1484,11 @@ struct i915_gem_mm { 
	struct llist_head free_list;

	struct work_struct free_work;



	/**

	 * Small stash of WC pages

	 */

	struct pagevec wc_stash;



	/** Usable portion of the GTT for GEM */

	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
@@ -1717,7 +1742,7 @@ struct intel_vbt_data { 
	int crt_ddc_pin;



	int child_dev_num;

	union child_device_config *child_dev;

	struct child_device_config *child_dev;



	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];

	struct sdvo_device_mapping sdvo_mappings[2];
@@ -2328,7 +2353,8 @@ struct drm_i915_private { 
	struct mutex dpll_lock;



	unsigned int active_crtcs;

	unsigned int min_pixclk[I915_MAX_PIPES];

	/* minimum acceptable cdclk for each pipe */

	int min_cdclk[I915_MAX_PIPES];



	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
@@ -2861,9 +2887,8 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)

#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)

#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)

#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \

				 INTEL_DEVID(dev_priv) == 0x0152 || \

				 INTEL_DEVID(dev_priv) == 0x015a)

#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \

				 (dev_priv)->info.gt == 1)

#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)

#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)

#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
@@ -2885,11 +2910,11 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)

#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

				 (dev_priv)->info.gt == 3)

#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)

#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

				 (dev_priv)->info.gt == 3)

/* ULX machines are also considered ULT. */

#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \

				 INTEL_DEVID(dev_priv) == 0x0A1E)
@@ -2910,15 +2935,15 @@ intel_info(const struct drm_i915_private *dev_priv) 
				 INTEL_DEVID(dev_priv) == 0x5915 || \

				 INTEL_DEVID(dev_priv) == 0x591E)

#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)

				 (dev_priv)->info.gt == 2)

#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

				 (dev_priv)->info.gt == 3)

#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)

				 (dev_priv)->info.gt == 4)

#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)

				 (dev_priv)->info.gt == 2)

#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

				 (dev_priv)->info.gt == 3)

#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
@@ -3647,6 +3672,9 @@ i915_vm_to_ppgtt(struct i915_address_space *vm) 
/* i915_gem_fence_reg.c */

int __must_check i915_vma_get_fence(struct i915_vma *vma);

int __must_check i915_vma_put_fence(struct i915_vma *vma);

struct drm_i915_fence_reg *

i915_reserve_fence(struct drm_i915_private *dev_priv);

void i915_unreserve_fence(struct drm_i915_fence_reg *fence);



void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);

void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
@@ -4332,11 +4360,4 @@ int remap_io_mapping(struct vm_area_struct *vma, 
		     unsigned long addr, unsigned long pfn, unsigned long size,

		     struct io_mapping *iomap);



static inline bool

intel_engine_can_store_dword(struct intel_engine_cs *engine)

{

	return __intel_engine_can_store_dword(INTEL_GEN(engine->i915),

					      engine->class);

}



#endif

drivers/gpu/drm/i915/i915_gem.c

+37 −35
Original line number Diff line number Diff line
@@ -1013,17 +1013,20 @@ gtt_user_read(struct io_mapping *mapping, 
	      loff_t base, int offset,

	      char __user *user_data, int length)

{

	void *vaddr;

	void __iomem *vaddr;

	unsigned long unwritten;



	/* We can use the cpu mem copy function because this is X86. */

	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);

	unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);

	vaddr = io_mapping_map_atomic_wc(mapping, base);

	unwritten = __copy_to_user_inatomic(user_data,

					    (void __force *)vaddr + offset,

					    length);

	io_mapping_unmap_atomic(vaddr);

	if (unwritten) {

		vaddr = (void __force *)

			io_mapping_map_wc(mapping, base, PAGE_SIZE);

		unwritten = copy_to_user(user_data, vaddr + offset, length);

		vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);

		unwritten = copy_to_user(user_data,

					 (void __force *)vaddr + offset,

					 length);

		io_mapping_unmap(vaddr);

	}

	return unwritten;
@@ -1189,18 +1192,18 @@ ggtt_write(struct io_mapping *mapping, 
	   loff_t base, int offset,

	   char __user *user_data, int length)

{

	void *vaddr;

	void __iomem *vaddr;

	unsigned long unwritten;



	/* We can use the cpu mem copy function because this is X86. */

	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);

	unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,

	vaddr = io_mapping_map_atomic_wc(mapping, base);

	unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,

						      user_data, length);

	io_mapping_unmap_atomic(vaddr);

	if (unwritten) {

		vaddr = (void __force *)

			io_mapping_map_wc(mapping, base, PAGE_SIZE);

		unwritten = copy_from_user(vaddr + offset, user_data, length);

		vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);

		unwritten = copy_from_user((void __force *)vaddr + offset,

					   user_data, length);

		io_mapping_unmap(vaddr);

	}
@@ -2476,8 +2479,6 @@ static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) 
{

	struct sg_table *pages;



	GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));



	if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {

		DRM_DEBUG("Attempting to obtain a purgeable object\n");

		return -EFAULT;
@@ -2507,6 +2508,8 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) 
		return err;



	if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {

		GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));



		err = ____i915_gem_object_get_pages(obj);

		if (err)

			goto unlock;
@@ -2590,6 +2593,8 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, 


	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {

		if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {

			GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));



			ret = ____i915_gem_object_get_pages(obj);

			if (ret)

				goto err_unlock;
@@ -3257,11 +3262,11 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) 
		struct i915_gem_context *ctx = lut->ctx;

		struct i915_vma *vma;



		GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));

		if (ctx->file_priv != fpriv)

			continue;



		vma = radix_tree_delete(&ctx->handles_vma, lut->handle);



		GEM_BUG_ON(vma->obj != obj);



		/* We allow the process to have multiple handles to the same
@@ -3375,26 +3380,14 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) 
	return 0;

}



static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)

{

	return wait_for(intel_engine_is_idle(engine), timeout_ms);

}



static int wait_for_engines(struct drm_i915_private *i915)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;



	for_each_engine(engine, i915, id) {

		if (GEM_WARN_ON(wait_for_engine(engine, 50))) {

	if (wait_for(intel_engines_are_idle(i915), 50)) {

		DRM_ERROR("Failed to idle engines, declaring wedged!\n");

		i915_gem_set_wedged(i915);

		return -EIO;

	}



		GEM_BUG_ON(intel_engine_get_seqno(engine) !=

			   intel_engine_last_submit(engine));

	}



	return 0;

}
@@ -4426,6 +4419,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, 
	llist_for_each_entry_safe(obj, on, freed, freed) {

		GEM_BUG_ON(obj->bind_count);

		GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));

		GEM_BUG_ON(!list_empty(&obj->lut_list));



		if (obj->ops->release)

			obj->ops->release(obj);
@@ -4533,6 +4527,12 @@ static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) 


void i915_gem_sanitize(struct drm_i915_private *i915)

{

	if (i915_terminally_wedged(&i915->gpu_error)) {

		mutex_lock(&i915->drm.struct_mutex);

		i915_gem_unset_wedged(i915);

		mutex_unlock(&i915->drm.struct_mutex);

	}



	/*

	 * If we inherit context state from the BIOS or earlier occupants

	 * of the GPU, the GPU may be in an inconsistent state when we
@@ -4572,7 +4572,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) 
	ret = i915_gem_wait_for_idle(dev_priv,

				     I915_WAIT_INTERRUPTIBLE |

				     I915_WAIT_LOCKED);

	if (ret)

	if (ret && ret != -EIO)

		goto err_unlock;



	assert_kernel_context_is_current(dev_priv);
@@ -4594,7 +4594,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) 
	 * reset the GPU back to its idle, low power state.

	 */

	WARN_ON(dev_priv->gt.awake);

	WARN_ON(!intel_engines_are_idle(dev_priv));

	if (WARN_ON(!intel_engines_are_idle(dev_priv)))

		i915_gem_set_wedged(dev_priv); /* no hope, discard everything */



	/*

	 * Neither the BIOS, ourselves or any other kernel
@@ -4616,11 +4617,12 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) 
	 * machine in an unusable condition.

	 */

	i915_gem_sanitize(dev_priv);

	goto out_rpm_put;



	intel_runtime_pm_put(dev_priv);

	return 0;



err_unlock:

	mutex_unlock(&dev->struct_mutex);

out_rpm_put:

	intel_runtime_pm_put(dev_priv);

	return ret;

}