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Commit 9a6330cf authored by Matthew Auld's avatar Matthew Auld Committed by Chris Wilson
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drm/i915: enable IPS bit for 64K pages 



Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.

v2: add comment mentioning that 64K is BDW+

v3: move to more suitable home

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-11-matthew.auld@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-10-chris@chris-wilson.co.uk
parent 855822be

drivers/gpu/drm/i915/i915_gem_gtt.c

+17 −0
Original line number Diff line number Diff line
@@ -1987,6 +1987,23 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) 
		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

	else if (IS_GEN9_LP(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);



	/*

	 * To support 64K PTEs we need to first enable the use of the

	 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical

	 * mmio, otherwise the page-walker will simply ignore the IPS bit. This

	 * shouldn't be needed after GEN10.

	 *

	 * 64K pages were first introduced from BDW+, although technically they

	 * only *work* from gen9+. For pre-BDW we instead have the option for

	 * 32K pages, but we don't currently have any support for it in our

	 * driver.

	 */

	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&

	    INTEL_GEN(dev_priv) <= 10)

		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,

			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |

			   GAMW_ECO_ENABLE_64K_IPS_FIELD);

}



int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -2371,6 +2371,9 @@ enum i915_power_well_id { 
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)

#define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1<<18)



#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)

#define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF



#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)

#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)

#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1<<24)