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Commit 97be8ab2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.16-next-dts64' of... 

Merge tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

Pull "ARM: mediatek: dts64 updates for v4.16-next" from Matthias Brugger:

- mt2712e add auxadc devcie

mt7622:
- fix clock bindings description
- add nodes for mmc, usb, SATA, PCI, ethernet, cpufreq, PMIC mt6380,
pinctrl, scpsys and clock devices

* tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt2712: Add auxadc device node.
  dt-bindings: clock: mediatek: add missing required #reset-cells
  arm64: dts: mt7622: add mmc related device nodes
  arm64: dts: mt7622: add usb device nodes
  arm64: dts: mt7622: add SATA device nodes
  arm64: dts: mt7622: add PCIe device nodes
  arm64: dts: mt7622: add ethernet device nodes
  arm64: dts: mt7622: add flash related device nodes
  arm64: dts: mt7622: add SoC and peripheral related device nodes
  arm64: dts: mt7622: turn uart0 clock to real ones
  arm64: dts: mt7622: add cpufreq related device nodes
  arm64: dts: mt7622: add PMIC MT6380 related nodes
  arm64: dts: mt7622: add pinctrl related device nodes
  arm64: dts: mt7622: add power domain controller device nodes
  arm64: dts: mt7622: add clock controller device nodes
parents 00730c5b 5f599552

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required Properties: 
	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt7622-ethsys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The ethsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 
- compatible: Should be:

	- "mediatek,mt7622-pciesys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The PCIESYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { 
	compatible = "mediatek,mt7622-pciesys", "syscon";

	reg = <0 0x1a100800 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 
- compatible: Should be:

	- "mediatek,mt7622-ssusbsys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The SSUSBSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { 
	compatible = "mediatek,mt7622-ssusbsys", "syscon";

	reg = <0 0x1a000000 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

arch/arm64/boot/dts/mediatek/mt2712-evb.dts

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ 


};



&auxadc {

	status = "okay";

};



&cpu0 {

	proc-supply = <&cpus_fixed_vproc0>;

};

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -289,6 +289,15 @@ 
			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	auxadc: adc@11001000 {

		compatible = "mediatek,mt2712-auxadc";

		reg = <0 0x11001000 0 0x1000>;

		clocks = <&pericfg CLK_PERI_AUXADC>;

		clock-names = "main";

		#io-channel-cells = <1>;

		status = "disabled";

	};



	uart0: serial@11002000 {

		compatible = "mediatek,mt2712-uart",

			     "mediatek,mt6577-uart";