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Commit 00730c5b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.16-next-dts32' of... 

Merge tag 'v4.16-next-dts32' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

Pull "ARM: mediatek: dts32 updates for v4.16-next" from Matthias Brugger:

mt7623:
- fix style issues of the dts
- add cpu clock properties
- add PCI controller
- add mt7623 reference board

banapi-r2:
- enable missing uarts
- fix regulator for mmc
- fix USB initialization

* tag 'v4.16-next-dts32' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm: dts: mt7623: add PCIe related nodes
  arm: dts: mt7623: use - instead of _ in DT node name
  arm: dts: mt7623: remove useless property pinctrl-names at node switch@0
  arm: dts: mt7623: add related clock properties to cpu[1-3] nodes
  arm: dts: mt7623: enable three available UARTs on bananapi-r2
  arm: dts: mt7623: fix the regulators mmc should use on bananapi-r2
  arm: dts: mt7623: fix USB initialization fails on bananapi-r2
  dt-bindings: arm: mediatek: add support for more mt7623 reference boards
parents 7c006f5e c10a98c4

Documentation/devicetree/bindings/arm/mediatek.txt

+9 −0
Original line number Diff line number Diff line
@@ -50,6 +50,15 @@ Supported boards: 
- Reference board variant 1 for MT7622:

    Required root node properties:

      - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";

- Reference board for MT7623a with eMMC:

    Required root node properties:

      - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";

- Reference board for MT7623a with NAND:

    Required root node properties:

      - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";

- Reference board for MT7623n with eMMC:

    Required root node properties:

      - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";

- Reference  board for MT7623n with NAND:

    Required root node properties:

      - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";

arch/arm/boot/dts/mt7623.dtsi

+120 −6
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
	compatible = "mediatek,mt7623";

	interrupt-parent = <&sysirq>;



	cpu_opp_table: opp_table {

	cpu_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;
@@ -96,6 +96,9 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x1>;

			clocks = <&infracfg CLK_INFRA_CPUSEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";

			operating-points-v2 = <&cpu_opp_table>;

			clock-frequency = <1300000000>;

		};
@@ -104,6 +107,9 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x2>;

			clocks = <&infracfg CLK_INFRA_CPUSEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";

			operating-points-v2 = <&cpu_opp_table>;

			clock-frequency = <1300000000>;

		};
@@ -112,6 +118,9 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x3>;

			clocks = <&infracfg CLK_INFRA_CPUSEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";

			operating-points-v2 = <&cpu_opp_table>;

			clock-frequency = <1300000000>;

		};
@@ -138,32 +147,32 @@ 
	};



	thermal-zones {

			cpu_thermal: cpu_thermal {

			cpu_thermal: cpu-thermal {

				polling-delay-passive = <1000>;

				polling-delay = <1000>;



				thermal-sensors = <&thermal 0>;



				trips {

					cpu_passive: cpu_passive {

					cpu_passive: cpu-passive {

						temperature = <47000>;

						hysteresis = <2000>;

						type = "passive";

					};



					cpu_active: cpu_active {

					cpu_active: cpu-active {

						temperature = <67000>;

						hysteresis = <2000>;

						type = "active";

					};



					cpu_hot: cpu_hot {

					cpu_hot: cpu-hot {

						temperature = <87000>;

						hysteresis = <2000>;

						type = "hot";

					};



					cpu_crit {

					cpu-crit {

						temperature = <107000>;

						hysteresis = <2000>;

						type = "critical";
@@ -670,6 +679,111 @@ 
		#reset-cells = <1>;

	};



	pcie: pcie@1a140000 {

		compatible = "mediatek,mt7623-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */

		      <0 0x1a142000 0 0x1000>, /* Port0 registers */

		      <0 0x1a143000 0 0x1000>, /* Port1 registers */

		      <0 0x1a144000 0 0x1000>; /* Port2 registers */

		reg-names = "subsys", "port0", "port1", "port2";

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xf800 0 0 0>;

		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,

				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,

				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

			 <&hifsys CLK_HIFSYS_PCIE0>,

			 <&hifsys CLK_HIFSYS_PCIE1>,

			 <&hifsys CLK_HIFSYS_PCIE2>;

		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";

		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;

		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";

		phys = <&pcie0_port PHY_TYPE_PCIE>,

		       <&pcie1_port PHY_TYPE_PCIE>,

		       <&u3port1 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		bus-range = <0x00 0xff>;

		status = "disabled";

		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000

			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;



		pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

			status = "disabled";

		};



		pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

			status = "disabled";

		};



		pcie@2,0 {

			reg = <0x1000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

			status = "disabled";

		};

	};



	pcie0_phy: pcie-phy@1a149000 {

		compatible = "mediatek,generic-tphy-v1";

		reg = <0 0x1a149000 0 0x0700>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		status = "disabled";



		pcie0_port: pcie-phy@1a149900 {

			reg = <0 0x1a149900 0 0x0700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};

	};



	pcie1_phy: pcie-phy@1a14a000 {

		compatible = "mediatek,generic-tphy-v1";

		reg = <0 0x1a14a000 0 0x0700>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		status = "disabled";



		pcie1_port: pcie-phy@1a14a900 {

			reg = <0 0x1a14a900 0 0x0700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};

	};



	usb1: usb@1a1c0000 {

		compatible = "mediatek,mt7623-xhci",

			     "mediatek,mt8173-xhci";

arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts

+100 −33
Original line number Diff line number Diff line
@@ -39,7 +39,34 @@ 
		};

	};



	gpio_keys {

	reg_1p8v: regulator-1p8v {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-boot-on;

		regulator-always-on;

	};



	reg_3p3v: regulator-3p3v {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-boot-on;

		regulator-always-on;

	};



	reg_5v: regulator-5v {

		compatible = "regulator-fixed";

		regulator-name = "fixed-5V";

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;

		regulator-boot-on;

		regulator-always-on;

	};



	gpio-keys {

		compatible = "gpio-keys";

		pinctrl-names = "default";

		pinctrl-0 = <&key_pins_a>;
@@ -120,7 +147,6 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

			pinctrl-names = "default";

			reset-gpios = <&pio 33 0>;

			core-supply = <&mt6323_vpa_reg>;

			io-supply = <&mt6323_vemc3v3_reg>;
@@ -191,8 +217,8 @@ 
	bus-width = <8>;

	max-frequency = <50000000>;

	cap-mmc-highspeed;

	vmmc-supply = <&mt6323_vemc3v3_reg>;

	vqmmc-supply = <&mt6323_vio18_reg>;

	vmmc-supply = <&reg_3p3v>;

	vqmmc-supply = <&reg_1p8v>;

	non-removable;

};
@@ -205,20 +231,42 @@ 
	max-frequency = <50000000>;

	cap-sd-highspeed;

	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&mt6323_vmch_reg>;

	vqmmc-supply = <&mt6323_vio18_reg>;

	vmmc-supply = <&reg_3p3v>;

	vqmmc-supply = <&reg_3p3v>;

};



&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_default>;

	status = "okay";



	pcie@0,0 {

		status = "okay";

	};



	pcie@1,0 {

		status = "okay";

	};

};



&pcie0_phy {

	status = "okay";

};



&pcie1_phy {

	status = "okay";

};



&pio {

	cir_pins_a:cir@0 {

		pins_cir {

		pins-cir {

			pinmux = <MT7623_PIN_46_IR_FUNC_IR>;

			bias-disable;

		};

	};



	i2c0_pins_a: i2c@0 {

		pins_i2c0 {

		pins-i2c0 {

			pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,

				 <MT7623_PIN_76_SCL0_FUNC_SCL0>;

			bias-disable;
@@ -226,7 +274,7 @@ 
	};



	i2c1_pins_a: i2c@1 {

		pin_i2c1 {

		pin-i2c1 {

			pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,

				 <MT7623_PIN_58_SCL1_FUNC_SCL1>;

			bias-disable;
@@ -234,7 +282,7 @@ 
	};



	i2s0_pins_a: i2s@0 {

		pin_i2s0 {

		pin-i2s0 {

			pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,

				 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,

				 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
@@ -246,7 +294,7 @@ 
	};



	i2s1_pins_a: i2s@1 {

		pin_i2s1 {

		pin-i2s1 {

			pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,

				 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,

				 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
@@ -258,7 +306,7 @@ 
	};



	key_pins_a: keys@0 {

		pins_keys {

		pins-keys {

			pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,

				 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;

			input-enable;
@@ -266,7 +314,7 @@ 
	};



	led_pins_a: leds@0 {

		pins_leds {

		pins-leds {

			pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,

				 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,

				 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
@@ -274,7 +322,7 @@ 
	};



	mmc0_pins_default: mmc0default {

		pins_cmd_dat {

		pins-cmd-dat {

			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,

				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,

				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -288,19 +336,19 @@ 
			bias-pull-up;

		};



		pins_clk {

		pins-clk {

			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;

			bias-pull-down;

		};



		pins_rst {

		pins-rst {

			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;

			bias-pull-up;

		};

	};



	mmc0_pins_uhs: mmc0 {

		pins_cmd_dat {

		pins-cmd-dat {

			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,

				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,

				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -315,20 +363,20 @@ 
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;

		};



		pins_clk {

		pins-clk {

			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;

			drive-strength = <MTK_DRIVE_2mA>;

			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;

		};



		pins_rst {

		pins-rst {

			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;

			bias-pull-up;

		};

	};



	mmc1_pins_default: mmc1default {

		pins_cmd_dat {

		pins-cmd-dat {

			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,

				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,

				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -339,26 +387,26 @@ 
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;

		};



		pins_clk {

		pins-clk {

			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;

			bias-pull-down;

			drive-strength = <MTK_DRIVE_4mA>;

		};



		pins_wp {

		pins-wp {

			pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;

			input-enable;

			bias-pull-up;

		};



		pins_insert {

		pins-insert {

			pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;

			bias-pull-up;

		};

	};



	mmc1_pins_uhs: mmc1 {

		pins_cmd_dat {

		pins-cmd-dat {

			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,

				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,

				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -369,15 +417,23 @@ 
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;

		};



		pins_clk {

		pins-clk {

			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;

			drive-strength = <MTK_DRIVE_4mA>;

			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;

		};

	};



	pcie_default: pcie_pin_default {

		pins_cmd_dat {

			pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,

				 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;

			bias-disable;

		};

	};



	pwm_pins_a: pwm@0 {

		pins_pwm {

		pins-pwm {

			pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,

				 <MT7623_PIN_204_PWM1_FUNC_PWM1>,

				 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
@@ -387,7 +443,7 @@ 
	};



	spi0_pins_a: spi@0 {

		pins_spi {

		pins-spi {

			pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,

				<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,

				<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
@@ -397,18 +453,25 @@ 
	};



	uart0_pins_a: uart@0 {

		pins_dat {

		pins-dat {

			pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,

				 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;

		};

	};



	uart1_pins_a: uart@1 {

		pins_dat {

		pins-dat {

			pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,

				 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;

		};

	};



	uart2_pins_a: uart@2 {

		pins-dat {

			pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,

				 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;

		};

	};

};



&pwm {
@@ -454,26 +517,30 @@ 
&uart0 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart0_pins_a>;

	status = "disabled";

	status = "okay";

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_pins_a>;

	status = "disabled";

	status = "okay";

};



&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart2_pins_a>;

	status = "okay";

};



&usb1 {

	vusb33-supply = <&mt6323_vusb_reg>;

	vusb33-supply = <&reg_3p3v>;

	vbus-supply = <&reg_5v>;

	status = "okay";

};



&usb2 {

	vusb33-supply = <&mt6323_vusb_reg>;

	vusb33-supply = <&reg_3p3v>;

	vbus-supply = <&reg_5v>;

	status = "okay";

};

arch/arm/boot/dts/mt7623n-rfb-nand.dts

+3 −3
Original line number Diff line number Diff line
@@ -81,13 +81,13 @@ 


&pio {

	nand_pins_default: nanddefault {

		pins_ale {

		pins-ale {

			pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;

			drive-strength = <MTK_DRIVE_8mA>;

			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;

		};



		pins_dat {

		pins-dat {

			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,

				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,

				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
@@ -102,7 +102,7 @@ 
			bias-pull-up;

		};



		pins_we {

		pins-we {

			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;

			drive-strength = <MTK_DRIVE_8mA>;

			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;