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Commit 946edc47 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux 

Pull ux500 clk fixes from Mike Turquette:
 "Missing clkdev entries are causing regressions on the U8500 platform.
  This pull request contains those missing clkdev entries which are
  needed to boot that platform."

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
  clk: ux500: Register slimbus clock lookups for u8500
  clk: ux500: Update rtc clock lookup for u8500
  clk: ux500: Register msp clock lookups for u8500
  clk: ux500: Register ssp clock lookups for u8500
  clk: ux500: Register i2c clock lookups for u8500
parents 70c80dfd 3d930678

drivers/clk/ux500/u8500_clk.c

+46 −4
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ void u8500_clk_init(void) 
				CLK_IS_ROOT|CLK_IGNORE_UNUSED,

				32768);

	clk_register_clkdev(clk, "clk32k", NULL);

	clk_register_clkdev(clk, NULL, "rtc-pl031");

	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");



	/* PRCMU clocks */

	fw_version = prcmu_get_fw_version();
@@ -228,10 +228,17 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,

				BIT(2), 0);

	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");



	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,

				BIT(3), 0);

	clk_register_clkdev(clk, "apb_pclk", "msp0");

	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");



	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,

				BIT(4), 0);

	clk_register_clkdev(clk, "apb_pclk", "msp1");

	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");



	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,

				BIT(5), 0);
@@ -239,6 +246,7 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,

				BIT(6), 0);

	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");



	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,

				BIT(7), 0);
@@ -246,6 +254,7 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,

				BIT(8), 0);

	clk_register_clkdev(clk, "apb_pclk", "slimbus0");



	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,

				BIT(9), 0);
@@ -255,11 +264,16 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,

				BIT(10), 0);

	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");



	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,

				BIT(11), 0);

	clk_register_clkdev(clk, "apb_pclk", "msp3");

	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");



	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,

				BIT(0), 0);

	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");



	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,

				BIT(1), 0);
@@ -279,12 +293,13 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,

				BIT(5), 0);

	clk_register_clkdev(clk, "apb_pclk", "msp2");

	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");



	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,

				BIT(6), 0);

	clk_register_clkdev(clk, "apb_pclk", "sdi1");





	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,

				BIT(7), 0);

	clk_register_clkdev(clk, "apb_pclk", "sdi3");
@@ -316,10 +331,15 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,

				BIT(1), 0);

	clk_register_clkdev(clk, "apb_pclk", "ssp0");



	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,

				BIT(2), 0);

	clk_register_clkdev(clk, "apb_pclk", "ssp1");



	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,

				BIT(3), 0);

	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");



	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,

				BIT(4), 0);
@@ -401,10 +421,17 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",

			U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "nmk-i2c.1");



	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",

			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "msp0");

	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");



	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",

			U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "msp1");

	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");



	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",

			U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
@@ -412,17 +439,25 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",

			U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "nmk-i2c.2");



	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",

			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);

	/* FIXME: Redefinition of BIT(3). */

			U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "slimbus0");



	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",

			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "nmk-i2c.4");



	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",

			U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "msp3");

	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");



	/* Periph2 */

	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",

			U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "nmk-i2c.3");



	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",

			U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
@@ -430,6 +465,8 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",

			U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "msp2");

	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");



	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",

			U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
@@ -450,10 +487,15 @@ void u8500_clk_init(void) 
	/* Periph3 */

	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",

			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "ssp0");



	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",

			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "ssp1");



	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",

			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "nmk-i2c.0");



	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",

			U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);