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Commit 3d930678 authored by Ulf Hansson's avatar Ulf Hansson Committed by Mike Turquette
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clk: ux500: Register slimbus clock lookups for u8500 



At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.

Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent d4915cf5

drivers/clk/ux500/u8500_clk.c

+3 −2
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,

				BIT(8), 0);

	clk_register_clkdev(clk, "apb_pclk", "slimbus0");



	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,

				BIT(9), 0);
@@ -441,8 +442,8 @@ void u8500_clk_init(void) 
	clk_register_clkdev(clk, NULL, "nmk-i2c.2");



	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",

			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);

	/* FIXME: Redefinition of BIT(3). */

			U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "slimbus0");



	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",

			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);