Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 939994da authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Pass crtc state to i9xx_enable_pll() 



Pass the crtc state to i9xx_enable_pll() and use it rather than
crtc->config.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913140900.6972-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent dfa311f0

drivers/gpu/drm/i915/intel_display.c

+5 −4
Original line number Diff line number Diff line
@@ -1568,11 +1568,12 @@ static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) 
	return count;

}



static void i9xx_enable_pll(struct intel_crtc *crtc)

static void i9xx_enable_pll(struct intel_crtc *crtc,

			    const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	i915_reg_t reg = DPLL(crtc->pipe);

	u32 dpll = crtc->config->dpll_hw_state.dpll;

	u32 dpll = crtc_state->dpll_hw_state.dpll;

	int i;



	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1609,7 +1610,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) 


	if (INTEL_GEN(dev_priv) >= 4) {

		I915_WRITE(DPLL_MD(crtc->pipe),

			   crtc->config->dpll_hw_state.dpll_md);

			   crtc_state->dpll_hw_state.dpll_md);

	} else {

		/* The pixel multiplier can only be updated once the

		 * DPLL is enabled and the clocks are stable.
@@ -5895,7 +5896,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, 


	intel_encoders_pre_enable(crtc, pipe_config, old_state);



	i9xx_enable_pll(intel_crtc);

	i9xx_enable_pll(intel_crtc, pipe_config);



	i9xx_pfit_enable(intel_crtc);