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Commit dfa311f0 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Parametrize CBR_DPLLBMD_PIPE defines 



Apply a bit of polish by parametrizing the CBR_DPLLBMD_PIPE defines.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913140900.6972-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent ecf837d9

drivers/gpu/drm/i915/i915_reg.h

+1 −2
Original line number Diff line number Diff line
@@ -5684,8 +5684,7 @@ enum { 
#define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)



#define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)

#define  CBR_DPLLBMD_PIPE_C		(1<<29)

#define  CBR_DPLLBMD_PIPE_B		(1<<18)

#define  CBR_DPLLBMD_PIPE(pipe)		(1<<(7+(pipe)*11)) /* pipes B and C */



/* FIFO watermark sizes etc */

#define G4X_FIFO_LINE_SIZE	64

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -1539,7 +1539,7 @@ static void chv_enable_pll(struct intel_crtc *crtc, 
		 * DPLLCMD is AWOL. Use chicken bits to propagate

		 * the value from DPLLBMD to either pipe B or C.

		 */

		I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);

		I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

		I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);

		I915_WRITE(CBR4_VLV, 0);

		dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;