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Commit 8cb09836 authored by Matthew Auld's avatar Matthew Auld Committed by Chris Wilson
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drm/i915: disable GTT cache for 2M pages 



When SW enables the use of 2M/1G pages, it must disable the GTT cache.

v2: don't disable for Cherryview which doesn't even support 48b PPGTT!

v3: explicitly check that the system does support 2M/1G pages

v4: split WA and decision logic

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-12-matthew.auld@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-11-chris@chris-wilson.co.uk
parent 9a6330cf

drivers/gpu/drm/i915/intel_pm.c

+5 −6
Original line number Diff line number Diff line
@@ -8453,6 +8453,9 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv) 


static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)

{

	/* The GTT cache must be disabled if the system is using 2M pages. */

	bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,

						 I915_GTT_PAGE_SIZE_2M);

	enum pipe pipe;



	ilk_init_lp_watermarks(dev_priv);
@@ -8487,12 +8490,8 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) 
	/* WaProgramL3SqcReg1Default:bdw */

	gen8_set_l3sqc_credits(dev_priv, 30, 2);



	/*

	 * WaGttCachingOffByDefault:bdw

	 * GTT cache may not work with big pages, so if those

	 * are ever enabled GTT cache may need to be disabled.

	 */

	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);

	/* WaGttCachingOffByDefault:bdw */

	I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);



	/* WaKVMNotificationOnConfigChange:bdw */

	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)