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Commit 7bcd3425 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "A rather small set of irq updates this time:

   - removal of the old and now obsolete irq domain debugging code

   - the new Goldfish PIC driver

   - the usual pile of small fixes and updates"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqdomain: Kill CONFIG_IRQ_DOMAIN_DEBUG
  irq/work: Improve the flag definitions
  irqchip/gic-v3: Fix the driver probe() fail due to disabled GICC entry
  irqchip/irq-goldfish-pic: Add Goldfish PIC driver
  dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver
  irqchip/ompic: fix return value check in ompic_of_init()
  dt-bindings/bcm283x: Define polarity of per-cpu interrupts
  irqchip/irq-bcm2836: Add support for DT interrupt polarity
  dt-bindings/bcm2836-l1-intc: Add interrupt polarity support
parents d0bd31dc c5baa1be

Documentation/IRQ-domain.txt

+2 −34
Original line number Diff line number Diff line
@@ -265,37 +265,5 @@ support other architectures, such as ARM, ARM64 etc. 


=== Debugging ===



If you switch on CONFIG_IRQ_DOMAIN_DEBUG (which depends on

CONFIG_IRQ_DOMAIN and CONFIG_DEBUG_FS), you will find a new file in

your debugfs mount point, called irq_domain_mapping. This file

contains a live snapshot of all the IRQ domains in the system:



 name              mapped  linear-max  direct-max  devtree-node

 pl061                  8           8           0  /smb/gpio@e0080000

 pl061                  8           8           0  /smb/gpio@e1050000

 pMSI                   0           0           0  /interrupt-controller@e1101000/v2m@e0080000

 MSI                   37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2m                37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2                448         448           0  /interrupt-controller@e1101000



it also iterates over the interrupts to display their mapping in the

domains, and makes the domain stacking visible:





irq    hwirq    chip name        chip data           active  type            domain

    1  0x00019  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    2  0x0001d  GICv2            0xffff00000916bfd8          LINEAR          GICv2

    3  0x0001e  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    4  0x0001b  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    5  0x0001a  GICv2            0xffff00000916bfd8          LINEAR          GICv2

[...]

   96  0x81808  MSI              0x          (null)           RADIX          MSI

   96+ 0x00063  GICv2m           0xffff8003ee116980           RADIX          GICv2m

   96+ 0x00063  GICv2            0xffff00000916bfd8          LINEAR          GICv2

   97  0x08800  MSI              0x          (null)     *     RADIX          MSI

   97+ 0x00064  GICv2m           0xffff8003ee116980     *     RADIX          GICv2m

   97+ 0x00064  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2



Here, interrupts 1-5 are only using a single domain, while 96 and 97

are build out of a stack of three domain, each level performing a

particular function.
 
Most of the internals of the IRQ subsystem are exposed in debugfs by

turning CONFIG_GENERIC_IRQ_DEBUGFS on.

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt

+2 −2
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ Required properties: 
			  registers

- interrupt-controller:	Identifies the node as an interrupt controller

- #interrupt-cells:	Specifies the number of cells needed to encode an

			  interrupt source. The value shall be 1

			  interrupt source. The value shall be 2



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.
@@ -32,6 +32,6 @@ local_intc: local_intc { 
	compatible = "brcm,bcm2836-l1-intc";

	reg = <0x40000000 0x100>;

	interrupt-controller;

	#interrupt-cells = <1>;

	#interrupt-cells = <2>;

	interrupt-parent = <&local_intc>;

};

Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt

0 → 100644
+30 −0
Original line number Diff line number Diff line 
Android Goldfish PIC



Android Goldfish programmable interrupt device used by Android

emulator.



Required properties:



- compatible : should contain "google,goldfish-pic"

- reg        : <registers mapping>

- interrupts : <interrupt mapping>



Example for mips when used in cascade mode:



        cpuintc {

                #interrupt-cells = <0x1>;

                #address-cells = <0>;

                interrupt-controller;

                compatible = "mti,cpu-interrupt-controller";

        };



        interrupt-controller@1f000000 {

                compatible = "google,goldfish-pic";

                reg = <0x1f000000 0x1000>;



                interrupt-controller;

                #interrupt-cells = <0x1>;



                interrupt-parent = <&cpuintc>;

                interrupts = <0x2>;

        };

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -875,6 +875,12 @@ S: Supported 
F:	drivers/android/

F:	drivers/staging/android/



ANDROID GOLDFISH PIC DRIVER

M:	Miodrag Dinic <miodrag.dinic@mips.com>

S:	Supported

F:	Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt

F:	drivers/irqchip/irq-goldfish-pic.c



ANDROID GOLDFISH RTC DRIVER

M:	Miodrag Dinic <miodrag.dinic@mips.com>

S:	Supported

arch/arm/boot/dts/bcm2836.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -13,24 +13,24 @@ 
			compatible = "brcm,bcm2836-l1-intc";

			reg = <0x40000000 0x100>;

			interrupt-controller;

			#interrupt-cells = <1>;

			#interrupt-cells = <2>;

			interrupt-parent = <&local_intc>;

		};



		arm-pmu {

			compatible = "arm,cortex-a7-pmu";

			interrupt-parent = <&local_intc>;

			interrupts = <9>;

			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupt-parent = <&local_intc>;

		interrupts = <0>, // PHYS_SECURE_PPI

			     <1>, // PHYS_NONSECURE_PPI

			     <3>, // VIRT_PPI

			     <2>; // HYP_PPI

		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI

			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI

			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI

			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI

		always-on;

	};
@@ -76,7 +76,7 @@ 
	compatible = "brcm,bcm2836-armctrl-ic";

	reg = <0x7e00b200 0x200>;

	interrupt-parent = <&local_intc>;

	interrupts = <8>;

	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

};



&cpu_thermal {