Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c5baa1be authored by Marc Zyngier's avatar Marc Zyngier Committed by Thomas Gleixner
Browse files

irqdomain: Kill CONFIG_IRQ_DOMAIN_DEBUG 



CONFIG_IRQ_DOMAIN_DEBUG is similar to CONFIG_GENERIC_IRQ_DEBUGFS,
just with less information.

Spring cleanup time.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Yang Shunyong <shunyong.yang@hxt-semitech.com>
Link: https://lkml.kernel.org/r/20180117142647.23622-1-marc.zyngier@arm.com
parent 80023aea

Documentation/IRQ-domain.txt

+2 −34
Original line number Diff line number Diff line
@@ -265,37 +265,5 @@ support other architectures, such as ARM, ARM64 etc. 


=== Debugging ===



If you switch on CONFIG_IRQ_DOMAIN_DEBUG (which depends on

CONFIG_IRQ_DOMAIN and CONFIG_DEBUG_FS), you will find a new file in

your debugfs mount point, called irq_domain_mapping. This file

contains a live snapshot of all the IRQ domains in the system:



 name              mapped  linear-max  direct-max  devtree-node

 pl061                  8           8           0  /smb/gpio@e0080000

 pl061                  8           8           0  /smb/gpio@e1050000

 pMSI                   0           0           0  /interrupt-controller@e1101000/v2m@e0080000

 MSI                   37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2m                37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2                448         448           0  /interrupt-controller@e1101000



it also iterates over the interrupts to display their mapping in the

domains, and makes the domain stacking visible:





irq    hwirq    chip name        chip data           active  type            domain

    1  0x00019  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    2  0x0001d  GICv2            0xffff00000916bfd8          LINEAR          GICv2

    3  0x0001e  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    4  0x0001b  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    5  0x0001a  GICv2            0xffff00000916bfd8          LINEAR          GICv2

[...]

   96  0x81808  MSI              0x          (null)           RADIX          MSI

   96+ 0x00063  GICv2m           0xffff8003ee116980           RADIX          GICv2m

   96+ 0x00063  GICv2            0xffff00000916bfd8          LINEAR          GICv2

   97  0x08800  MSI              0x          (null)     *     RADIX          MSI

   97+ 0x00064  GICv2m           0xffff8003ee116980     *     RADIX          GICv2m

   97+ 0x00064  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2



Here, interrupts 1-5 are only using a single domain, while 96 and 97

are build out of a stack of three domain, each level performing a

particular function.
 
Most of the internals of the IRQ subsystem are exposed in debugfs by

turning CONFIG_GENERIC_IRQ_DEBUGFS on.

arch/arm/configs/aspeed_g4_defconfig

+0 −1
Original line number Diff line number Diff line 
CONFIG_KERNEL_XZ=y

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_IRQ_DOMAIN_DEBUG=y

CONFIG_NO_HZ_IDLE=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_LOG_BUF_SHIFT=14

arch/arm/configs/aspeed_g5_defconfig

+0 −1
Original line number Diff line number Diff line 
CONFIG_KERNEL_XZ=y

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_IRQ_DOMAIN_DEBUG=y

CONFIG_NO_HZ_IDLE=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_LOG_BUF_SHIFT=14

arch/arm/configs/hisi_defconfig

+0 −1
Original line number Diff line number Diff line 
CONFIG_IRQ_DOMAIN_DEBUG=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_BLK_DEV_INITRD=y

arch/arm/configs/multi_v7_defconfig

+0 −1
Original line number Diff line number Diff line 
CONFIG_SYSVIPC=y

CONFIG_FHANDLE=y

CONFIG_IRQ_DOMAIN_DEBUG=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_CGROUPS=y