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Commit 78cfa580 authored by Pandiyan, Dhinakaran's avatar Pandiyan, Dhinakaran Committed by Paulo Zanoni
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drm/i915/glk: Apply cdclk workaround for DP audio 



Implement the DP-Audio cdclk restriction for GLK, similar to what is
implemented for BDW and other GEN9 platforms. The max. pixel clock
adjustment for GLK, however factors in the 2 pixels per clock output that
GLK generates.

Separating min. cdclk and max. pixel_rate would be nicer, but let's
defer that to future and fix the GLK bug for now.

Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1488931972-2865-1-git-send-email-dhinakaran.pandiyan@intel.com
parent 9f7886d0

drivers/gpu/drm/i915/intel_cdclk.c

+11 −6
Original line number Original line Diff line number Diff line
@@ -1442,16 +1442,21 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, 
	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)

	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)

		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);

		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);





	/* BSpec says "Do not use DisplayPort with CDCLK less than

	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,

	 * 432 MHz, audio enabled, port width x4, and link rate

	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else

	 * HBR2 (5.4 GHz), or else there may be audio corruption or

	 * there may be audio corruption or screen corruption." This cdclk

	 * screen corruption."

	 * restriction for GLK is 316.8 MHz and since GLK can output two

	 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.

	 */

	 */

	if (intel_crtc_has_dp_encoder(crtc_state) &&

	if (intel_crtc_has_dp_encoder(crtc_state) &&

	    crtc_state->has_audio &&

	    crtc_state->has_audio &&

	    crtc_state->port_clock >= 540000 &&

	    crtc_state->port_clock >= 540000 &&

	    crtc_state->lane_count == 4)

	    crtc_state->lane_count == 4) {

		if (IS_GEMINILAKE(dev_priv))

			pixel_rate = max(2 * 316800, pixel_rate);

		else

			pixel_rate = max(432000, pixel_rate);

			pixel_rate = max(432000, pixel_rate);

	}





	return pixel_rate;

	return pixel_rate;

}

}