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Commit 76cbf066 authored by Gustavo Pimentel's avatar Gustavo Pimentel Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Replace magic number by defines 



Replace magic numbers by a self-explained define to ease human
comprehension.

Signed-off-by: default avatarGustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarJingoo Han <jingoohan1@gmail.com>
Acked-by: default avatarJoao Pinto <jpinto@synopsys.com>
parent 6995de21

drivers/pci/dwc/pcie-designware-host.c

+20 −14
Original line number Original line Diff line number Diff line
@@ -83,18 +83,23 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 
	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;

	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;





	for (i = 0; i < num_ctrls; i++) {

	for (i = 0; i < num_ctrls; i++) {

		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,

		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +

				    &val);

					(i * MSI_REG_CTRL_BLOCK_SIZE),

				    4, &val);

		if (!val)

		if (!val)

			continue;

			continue;





		ret = IRQ_HANDLED;

		ret = IRQ_HANDLED;

		pos = 0;

		pos = 0;

		while ((pos = find_next_bit((unsigned long *) &val, 32,

		while ((pos = find_next_bit((unsigned long *) &val,

					    pos)) != 32) {

					    MAX_MSI_IRQS_PER_CTRL,

			irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);

					    pos)) != MAX_MSI_IRQS_PER_CTRL) {

			irq = irq_find_mapping(pp->irq_domain,

					       (i * MAX_MSI_IRQS_PER_CTRL) +

					       pos);

			generic_handle_irq(irq);

			generic_handle_irq(irq);

			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12,

			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS +

						(i * MSI_REG_CTRL_BLOCK_SIZE),

					    4, 1 << pos);

					    4, 1 << pos);

			pos++;

			pos++;

		}

		}
@@ -157,9 +162,9 @@ static void dw_pci_bottom_mask(struct irq_data *data) 
	if (pp->ops->msi_clear_irq) {

	if (pp->ops->msi_clear_irq) {

		pp->ops->msi_clear_irq(pp, data->hwirq);

		pp->ops->msi_clear_irq(pp, data->hwirq);

	} else {

	} else {

		ctrl = data->hwirq / 32;

		ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;

		res = ctrl * 12;

		res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

		bit = data->hwirq % 32;

		bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;





		pp->irq_status[ctrl] &= ~(1 << bit);

		pp->irq_status[ctrl] &= ~(1 << bit);

		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,

		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
@@ -180,9 +185,9 @@ static void dw_pci_bottom_unmask(struct irq_data *data) 
	if (pp->ops->msi_set_irq) {

	if (pp->ops->msi_set_irq) {

		pp->ops->msi_set_irq(pp, data->hwirq);

		pp->ops->msi_set_irq(pp, data->hwirq);

	} else {

	} else {

		ctrl = data->hwirq / 32;

		ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;

		res = ctrl * 12;

		res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

		bit = data->hwirq % 32;

		bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;





		pp->irq_status[ctrl] |= 1 << bit;

		pp->irq_status[ctrl] |= 1 << bit;

		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,

		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
@@ -652,8 +657,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 




	/* Initialize IRQ Status array */

	/* Initialize IRQ Status array */

	for (ctrl = 0; ctrl < num_ctrls; ctrl++)

	for (ctrl = 0; ctrl < num_ctrls; ctrl++)

		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,

		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE +

				    &pp->irq_status[ctrl]);

					(ctrl * MSI_REG_CTRL_BLOCK_SIZE),

				    4, &pp->irq_status[ctrl]);





	/* Setup RC BARs */

	/* Setup RC BARs */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);

drivers/pci/dwc/pcie-designware.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -110,6 +110,7 @@ 
#define MAX_MSI_IRQS			256

#define MAX_MSI_IRQS			256

#define MAX_MSI_IRQS_PER_CTRL		32

#define MAX_MSI_IRQS_PER_CTRL		32

#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)

#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)

#define MSI_REG_CTRL_BLOCK_SIZE		12

#define MSI_DEF_NUM_VECTORS		32

#define MSI_DEF_NUM_VECTORS		32





/* Maximum number of inbound/outbound iATUs */

/* Maximum number of inbound/outbound iATUs */