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Commit 754270c7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next 

First feature pull for 4.15.  Highlights:
- Per VM BO support
- Lots of powerplay cleanups
- Powerplay support for CI
- pasid mgr for kfd
- interrupt infrastructure for recoverable page faults
- SR-IOV fixes
- initial GPU reset for vega10
- prime mmap support
- ttm page table debugging improvements
- lots of bug fixes

* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (232 commits)
  drm/amdgpu: clarify license in amdgpu_trace_points.c
  drm/amdgpu: Add gem_prime_mmap support
  drm/amd/powerplay: delete dead code in smumgr
  drm/amd/powerplay: delete SMUM_FIELD_MASK
  drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_READ_FIELD
  drm/amd/powerplay: delete SMUM_SET_FIELD
  drm/amd/powerplay: delete SMUM_READ_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
  drm/amd/powerplay: delete SMUM_WRITE_FIELD
  drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD
  drm/amd/powerplay: move macros to hwmgr.h
  drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h
  drm/amd/powerplay: move SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL to hwmgr.h
  drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.h
  drm/amd/powerplay: add new helper functions in hwmgr.h
  drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair
  drm/amd/powerplay: refine powerplay code.
  drm/amd/powerplay: delete dead code in hwmgr.h
  drm/amd/powerplay: refine interface in struct pp_smumgr_func
  ...
parents 9afafdbf 6f87a895

drivers/gpu/drm/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ config DRM_AMDGPU 
	select BACKLIGHT_CLASS_DEVICE

	select BACKLIGHT_LCD_SUPPORT

	select INTERVAL_TREE

	select CHASH

	help

	  Choose this option if you have a recent AMD Radeon graphics card.
@@ -191,6 +192,8 @@ config DRM_AMDGPU 


source "drivers/gpu/drm/amd/amdgpu/Kconfig"



source "drivers/gpu/drm/amd/lib/Kconfig"



source "drivers/gpu/drm/nouveau/Kconfig"



source "drivers/gpu/drm/i915/Kconfig"

drivers/gpu/drm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ obj-$(CONFIG_DRM_ARM) += arm/ 
obj-$(CONFIG_DRM_TTM)	+= ttm/

obj-$(CONFIG_DRM_TDFX)	+= tdfx/

obj-$(CONFIG_DRM_R128)	+= r128/

obj-y			+= amd/lib/

obj-$(CONFIG_HSA_AMD) += amd/amdkfd/

obj-$(CONFIG_DRM_RADEON)+= radeon/

obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/

drivers/gpu/drm/amd/amdgpu/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -133,5 +133,3 @@ include $(FULL_AMD_PATH)/powerplay/Makefile 
amdgpu-y += $(AMD_POWERPLAY_FILES)



obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
 


CFLAGS_amdgpu_trace_points.o := -I$(src)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+37 −43
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ 
#include "amdgpu_uvd.h"

#include "amdgpu_vce.h"

#include "amdgpu_vcn.h"

#include "amdgpu_mn.h"



#include "gpu_scheduler.h"

#include "amdgpu_virt.h"
@@ -91,7 +92,7 @@ extern int amdgpu_dpm; 
extern int amdgpu_fw_load_type;

extern int amdgpu_aspm;

extern int amdgpu_runtime_pm;

extern unsigned amdgpu_ip_block_mask;

extern uint amdgpu_ip_block_mask;

extern int amdgpu_bapm;

extern int amdgpu_deep_color;

extern int amdgpu_vm_size;
@@ -104,14 +105,14 @@ extern int amdgpu_sched_jobs; 
extern int amdgpu_sched_hw_submission;

extern int amdgpu_no_evict;

extern int amdgpu_direct_gma_size;

extern unsigned amdgpu_pcie_gen_cap;

extern unsigned amdgpu_pcie_lane_cap;

extern unsigned amdgpu_cg_mask;

extern unsigned amdgpu_pg_mask;

extern unsigned amdgpu_sdma_phase_quantum;

extern uint amdgpu_pcie_gen_cap;

extern uint amdgpu_pcie_lane_cap;

extern uint amdgpu_cg_mask;

extern uint amdgpu_pg_mask;

extern uint amdgpu_sdma_phase_quantum;

extern char *amdgpu_disable_cu;

extern char *amdgpu_virtual_display;

extern unsigned amdgpu_pp_feature_mask;

extern uint amdgpu_pp_feature_mask;

extern int amdgpu_vram_page_split;

extern int amdgpu_ngg;

extern int amdgpu_prim_buf_per_se;
@@ -178,6 +179,7 @@ struct amdgpu_cs_parser; 
struct amdgpu_job;

struct amdgpu_irq_src;

struct amdgpu_fpriv;

struct amdgpu_bo_va_mapping;



enum amdgpu_cp_irq {

	AMDGPU_CP_IRQ_GFX_EOP = 0,
@@ -292,14 +294,25 @@ struct amdgpu_buffer_funcs { 


/* provided by hw blocks that can write ptes, e.g., sdma */

struct amdgpu_vm_pte_funcs {

	/* number of dw to reserve per operation */

	unsigned	copy_pte_num_dw;



	/* copy pte entries from GART */

	void (*copy_pte)(struct amdgpu_ib *ib,

			 uint64_t pe, uint64_t src,

			 unsigned count);



	/* write pte one entry at a time with addr mapping */

	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,

			  uint64_t value, unsigned count,

			  uint32_t incr);



	/* maximum nums of PTEs/PDEs in a single operation */

	uint32_t	set_max_nums_pte_pde;



	/* number of dw to reserve per operation */

	unsigned	set_pte_pde_num_dw;



	/* for linear pte/pde updates without addr mapping */

	void (*set_pte_pde)(struct amdgpu_ib *ib,

			    uint64_t pe,
@@ -332,6 +345,7 @@ struct amdgpu_gart_funcs { 
struct amdgpu_ih_funcs {

	/* ring read/write ptr handling, called from interrupt context */

	u32 (*get_wptr)(struct amdgpu_device *adev);

	bool (*prescreen_iv)(struct amdgpu_device *adev);

	void (*decode_iv)(struct amdgpu_device *adev,

			  struct amdgpu_iv_entry *entry);

	void (*set_rptr)(struct amdgpu_device *adev);
@@ -399,6 +413,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 
struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);

void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);

void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);

int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);

int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);



/* sub-allocation manager, it has to be protected by another lock.
@@ -457,6 +472,7 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev); 
int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,

			     int alignment, u32 initial_domain,

			     u64 flags, bool kernel,

			     struct reservation_object *resv,

			     struct drm_gem_object **obj);



int amdgpu_mode_dumb_create(struct drm_file *file_priv,
@@ -731,8 +747,8 @@ struct amdgpu_ctx_mgr { 
struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);

int amdgpu_ctx_put(struct amdgpu_ctx *ctx);



uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,

			      struct dma_fence *fence);

int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,

			      struct dma_fence *fence, uint64_t *seq);

struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,

				   struct amdgpu_ring *ring, uint64_t seq);
@@ -1014,7 +1030,6 @@ struct amdgpu_gfx { 
	/* reset mask */

	uint32_t                        grbm_soft_reset;

	uint32_t                        srbm_soft_reset;

	bool                            in_reset;

	/* s3/s4 mask */

	bool                            in_suspend;

	/* NGG */
@@ -1056,6 +1071,7 @@ struct amdgpu_cs_parser { 
	/* buffer objects */

	struct ww_acquire_ctx		ticket;

	struct amdgpu_bo_list		*bo_list;

	struct amdgpu_mn		*mn;

	struct amdgpu_bo_list_entry	vm_pd;

	struct list_head		validated;

	struct dma_fence		*fence;
@@ -1183,6 +1199,9 @@ struct amdgpu_firmware { 


	/* gpu info firmware data pointer */

	const struct firmware *gpu_info_fw;



	void *fw_buf_ptr;

	uint64_t fw_buf_mc;

};



/*
@@ -1196,20 +1215,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 
 */

void amdgpu_test_moves(struct amdgpu_device *adev);



/*

 * MMU Notifier

 */

#if defined(CONFIG_MMU_NOTIFIER)

int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);

void amdgpu_mn_unregister(struct amdgpu_bo *bo);

#else

static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)

{

	return -ENODEV;

}

static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}

#endif



/*

 * Debugfs

 */
@@ -1592,6 +1597,7 @@ struct amdgpu_device { 


	/* record last mm index being written through WREG32*/

	unsigned long last_mm_index;

	bool                            in_sriov_reset;

};



static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1759,6 +1765,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))

#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))

#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))

#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))

#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
@@ -1791,18 +1798,6 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 
				  u64 num_vis_bytes);

void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);

int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);

int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,

				     uint32_t flags);

bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);

struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);

bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,

				  unsigned long end);

bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,

				       int *last_invalidated);

bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);

uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,

				 struct ttm_mem_reg *mem);

void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);

void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);

void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
@@ -1885,10 +1880,9 @@ static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 
static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }

#endif



struct amdgpu_bo_va_mapping *

amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

		       uint64_t addr, struct amdgpu_bo **bo);

int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);

int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);



#include "amdgpu_object.h"

#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

+2 −0
Original line number Diff line number Diff line
@@ -169,6 +169,8 @@ static const struct kfd2kgd_calls kfd2kgd = { 
	.get_vmem_size = get_vmem_size,

	.get_gpu_clock_counter = get_gpu_clock_counter,

	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,

	.alloc_pasid = amdgpu_vm_alloc_pasid,

	.free_pasid = amdgpu_vm_free_pasid,

	.program_sh_mem_settings = kgd_program_sh_mem_settings,

	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,

	.init_pipeline = kgd_init_pipeline,