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Commit 690a3415 authored by David Daney's avatar David Daney Committed by Marc Zyngier
Browse files

arm64: Add workaround for Cavium Thunder erratum 30115 



Some Cavium Thunder CPUs suffer a problem where a KVM guest may
inadvertently cause the host kernel to quit receiving interrupts.

Use the Group-0/1 trapping in order to deal with it.

[maz]: Adapted patch to the Group-0/1 trapping, reworked commit log

Tested-by: default avatarAlexander Graf <agraf@suse.de>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
parent e982276d

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ stable kernels. 
| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |

| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |

| Cavium         | ThunderX SMMUv2 | #27704          | N/A                         |

| Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |

|                |                 |                 |                             |

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

|                |                 |                 |                             |

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -480,6 +480,17 @@ config CAVIUM_ERRATUM_27456 


	  If unsure, say Y.



config CAVIUM_ERRATUM_30115

	bool "Cavium erratum 30115: Guest may disable interrupts in host"

	default y

	help

	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through

	  1.2, and T83 Pass 1.0, KVM guest execution may disable

	  interrupts in host. Trapping both GICv3 group-0 and group-1

	  accesses sidesteps the issue.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -38,7 +38,8 @@ 
#define ARM64_WORKAROUND_REPEAT_TLBI		17

#define ARM64_WORKAROUND_QCOM_FALKOR_E1003	18

#define ARM64_WORKAROUND_858921			19

#define ARM64_WORKAROUND_CAVIUM_30115		20



#define ARM64_NCAPS				20

#define ARM64_NCAPS				21



#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+21 −0
Original line number Diff line number Diff line
@@ -132,6 +132,27 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_30115

	{

	/* Cavium ThunderX, T88 pass 1.x - 2.2 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		MIDR_RANGE(MIDR_THUNDERX, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 2),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),

	},

	{

	/* Cavium ThunderX, T83 pass 1.0 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),

	},

#endif

	{

		.desc = "Mismatched cache line size",

virt/kvm/arm/vgic/vgic-v3.c

+7 −0
Original line number Diff line number Diff line
@@ -501,6 +501,13 @@ int vgic_v3_probe(const struct gic_kvm_info *info) 
	if (kvm_vgic_global_state.vcpu_base == 0)

		kvm_info("disabling GICv2 emulation\n");



#ifdef CONFIG_ARM64

	if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {

		group0_trap = true;

		group1_trap = true;

	}

#endif



	if (group0_trap || group1_trap) {

		kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");

		static_branch_enable(&vgic_v3_cpuif_trap);