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Commit 6171de8f authored by Andrew Victor's avatar Andrew Victor Committed by Russell King
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[ARM] 3950/1: AT91: Split up system header file 



The AT91RM9200 system header file (at91rm9200_sys.h) has been split into
separate header files for each peripheral.  This was necessary since
some of the system peripherals are also used on AT91SAM9260 and
AT91SAM9261.

The new SAM9-specific register bits have also been defined.

Signed-off-by: default avatarAndrew Victor <andrew@sanpeople.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 62c1660d

include/asm-arm/arch-at91rm9200/at91_aic.h

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/*

 * include/asm-arm/arch-at91rm9200/at91_aic.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Advanced Interrupt Controller (AIC) - System peripherals registers.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_AIC_H

#define AT91_AIC_H



#define AT91_AIC_SMR(n)		(AT91_AIC + ((n) * 4))	/* Source Mode Registers 0-31 */

#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */

#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */

#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)

#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)

#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)

#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)



#define AT91_AIC_SVR(n)		(AT91_AIC + 0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */

#define AT91_AIC_IVR		(AT91_AIC + 0x100)	/* Interrupt Vector Register */

#define AT91_AIC_FVR		(AT91_AIC + 0x104)	/* Fast Interrupt Vector Register */

#define AT91_AIC_ISR		(AT91_AIC + 0x108)	/* Interrupt Status Register */

#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */



#define AT91_AIC_IPR		(AT91_AIC + 0x10c)	/* Interrupt Pending Register */

#define AT91_AIC_IMR		(AT91_AIC + 0x110)	/* Interrupt Mask Register */

#define AT91_AIC_CISR		(AT91_AIC + 0x114)	/* Core Interrupt Status Register */

#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */

#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */



#define AT91_AIC_IECR		(AT91_AIC + 0x120)	/* Interrupt Enable Command Register */

#define AT91_AIC_IDCR		(AT91_AIC + 0x124)	/* Interrupt Disable Command Register */

#define AT91_AIC_ICCR		(AT91_AIC + 0x128)	/* Interrupt Clear Command Register */

#define AT91_AIC_ISCR		(AT91_AIC + 0x12c)	/* Interrupt Set Command Register */

#define AT91_AIC_EOICR		(AT91_AIC + 0x130)	/* End of Interrupt Command Register */

#define AT91_AIC_SPU		(AT91_AIC + 0x134)	/* Spurious Interrupt Vector Register */

#define AT91_AIC_DCR		(AT91_AIC + 0x138)	/* Debug Control Register */

#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */

#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */



#define AT91_AIC_FFER		(AT91_AIC + 0x140)	/* Fast Forcing Enable Register [SAM9 only] */

#define AT91_AIC_FFDR		(AT91_AIC + 0x144)	/* Fast Forcing Disable Register [SAM9 only] */

#define AT91_AIC_FFSR		(AT91_AIC + 0x148)	/* Fast Forcing Status Register [SAM9 only] */



#endif

include/asm-arm/arch-at91rm9200/at91_dbgu.h

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/*

 * include/asm-arm/arch-at91rm9200/at91_dbgu.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Debug Unit (DBGU) - System peripherals registers.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_DBGU_H

#define AT91_DBGU_H



#define AT91_DBGU_CR		(AT91_DBGU + 0x00)	/* Control Register */

#define AT91_DBGU_MR		(AT91_DBGU + 0x04)	/* Mode Register */

#define AT91_DBGU_IER		(AT91_DBGU + 0x08)	/* Interrupt Enable Register */

#define		AT91_DBGU_TXRDY		(1 << 1)		/* Transmitter Ready */

#define		AT91_DBGU_TXEMPTY	(1 << 9)		/* Transmitter Empty */

#define AT91_DBGU_IDR		(AT91_DBGU + 0x0c)	/* Interrupt Disable Register */

#define AT91_DBGU_IMR		(AT91_DBGU + 0x10)	/* Interrupt Mask Register */

#define AT91_DBGU_SR		(AT91_DBGU + 0x14)	/* Status Register */

#define AT91_DBGU_RHR		(AT91_DBGU + 0x18)	/* Receiver Holding Register */

#define AT91_DBGU_THR		(AT91_DBGU + 0x1c)	/* Transmitter Holding Register */

#define AT91_DBGU_BRGR		(AT91_DBGU + 0x20)	/* Baud Rate Generator Register */



#define AT91_DBGU_CIDR		(AT91_DBGU + 0x40)	/* Chip ID Register */

#define AT91_DBGU_EXID		(AT91_DBGU + 0x44)	/* Chip ID Extension Register */

#define		AT91_CIDR_VERSION	(0x1f << 0)		/* Version of the Device */

#define		AT91_CIDR_EPROC		(7    << 5)		/* Embedded Processor */

#define		AT91_CIDR_NVPSIZ	(0xf  << 8)		/* Nonvolatile Program Memory Size */

#define		AT91_CIDR_NVPSIZ2	(0xf  << 12)		/* Second Nonvolatile Program Memory Size */

#define		AT91_CIDR_SRAMSIZ	(0xf  << 16)		/* Internal SRAM Size */

#define		AT91_CIDR_ARCH		(0xff << 20)		/* Architecture Identifier */

#define		AT91_CIDR_NVPTYP	(7    << 28)		/* Nonvolatile Program Memory Type */

#define		AT91_CIDR_EXT		(1    << 31)		/* Extension Flag */



#define AT91_DBGU_FNR		(AT91_DBGU + 0x48)	/* Force NTRST Register [SAM9 only] */

#define		AT91_DBGU_FNTRST	(1 << 0)		/* Force NTRST */



#endif

include/asm-arm/arch-at91rm9200/at91_pdc.h

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/*

 * include/asm-arm/arch-at91rm9200/at91_pdc.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Peripheral Data Controller (PDC) registers.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_PDC_H

#define AT91_PDC_H



#define AT91_PDC_RPR		0x100	/* Receive Pointer Register */

#define AT91_PDC_RCR		0x104	/* Receive Counter Register */

#define AT91_PDC_TPR		0x108	/* Transmit Pointer Register */

#define AT91_PDC_TCR		0x10c	/* Transmit Counter Register */

#define AT91_PDC_RNPR		0x110	/* Receive Next Pointer Register */

#define AT91_PDC_RNCR		0x114	/* Receive Next Counter Register */

#define AT91_PDC_TNPR		0x118	/* Transmit Next Pointer Register */

#define AT91_PDC_TNCR		0x11c	/* Transmit Next Counter Register */



#define AT91_PDC_PTCR		0x120	/* Transfer Control Register */

#define		AT91_PDC_RXTEN		(1 << 0)	/* Receiver Transfer Enable */

#define		AT91_PDC_RXTDIS		(1 << 1)	/* Receiver Transfer Disable */

#define		AT91_PDC_TXTEN		(1 << 8)	/* Transmitter Transfer Enable */

#define		AT91_PDC_TXTDIS		(1 << 9)	/* Transmitter Transfer Disable */



#define AT91_PDC_PTSR		0x124	/* Transfer Status Register */



#endif

include/asm-arm/arch-at91rm9200/at91_pio.h

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/*

 * include/asm-arm/arch-at91rm9200/at91_pio.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Parallel I/O Controller (PIO) - System peripherals registers.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_PIO_H

#define AT91_PIO_H



#define PIO_PER		0x00	/* Enable Register */

#define PIO_PDR		0x04	/* Disable Register */

#define PIO_PSR		0x08	/* Status Register */

#define PIO_OER		0x10	/* Output Enable Register */

#define PIO_ODR		0x14	/* Output Disable Register */

#define PIO_OSR		0x18	/* Output Status Register */

#define PIO_IFER	0x20	/* Glitch Input Filter Enable */

#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */

#define PIO_IFSR	0x28	/* Glitch Input Filter Status */

#define PIO_SODR	0x30	/* Set Output Data Register */

#define PIO_CODR	0x34	/* Clear Output Data Register */

#define PIO_ODSR	0x38	/* Output Data Status Register */

#define PIO_PDSR	0x3c	/* Pin Data Status Register */

#define PIO_IER		0x40	/* Interrupt Enable Register */

#define PIO_IDR		0x44	/* Interrupt Disable Register */

#define PIO_IMR		0x48	/* Interrupt Mask Register */

#define PIO_ISR		0x4c	/* Interrupt Status Register */

#define PIO_MDER	0x50	/* Multi-driver Enable Register */

#define PIO_MDDR	0x54	/* Multi-driver Disable Register */

#define PIO_MDSR	0x58	/* Multi-driver Status Register */

#define PIO_PUDR	0x60	/* Pull-up Disable Register */

#define PIO_PUER	0x64	/* Pull-up Enable Register */

#define PIO_PUSR	0x68	/* Pull-up Status Register */

#define PIO_ASR		0x70	/* Peripheral A Select Register */

#define PIO_BSR		0x74	/* Peripheral B Select Register */

#define PIO_ABSR	0x78	/* AB Status Register */

#define PIO_OWER	0xa0	/* Output Write Enable Register */

#define PIO_OWDR	0xa4	/* Output Write Disable Register */

#define PIO_OWSR	0xa8	/* Output Write Status Register */



#endif

include/asm-arm/arch-at91rm9200/at91_pmc.h

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/*

 * include/asm-arm/arch-at91rm9200/at91_pmc.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Power Management Controller (PMC) - System peripherals registers.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_PMC_H

#define AT91_PMC_H



#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */

#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */



#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */

#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */

#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */

#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */

#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */

#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */

#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */

#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */

#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */

#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */

#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */

#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */

#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */



#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */

#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */

#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */



#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register */

#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */

#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [AT91SAM926x only] */

#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */



#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */

#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */

#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */



#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */

#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */

#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */

#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */

#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */

#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */

#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */



#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */

#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */

#define			AT91_PMC_CSS_SLOW		(0 << 0)

#define			AT91_PMC_CSS_MAIN		(1 << 0)

#define			AT91_PMC_CSS_PLLA		(2 << 0)

#define			AT91_PMC_CSS_PLLB		(3 << 0)

#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */

#define 		AT91_PMC_PRES_1			(0 << 2)

#define			AT91_PMC_PRES_2			(1 << 2)

#define			AT91_PMC_PRES_4			(2 << 2)

#define			AT91_PMC_PRES_8			(3 << 2)

#define			AT91_PMC_PRES_16		(4 << 2)

#define			AT91_PMC_PRES_32		(5 << 2)

#define			AT91_PMC_PRES_64		(6 << 2)

#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */

#define			AT91_PMC_MDIV_1			(0 << 8)

#define			AT91_PMC_MDIV_2			(1 << 8)

#define			AT91_PMC_MDIV_3			(2 << 8)

#define			AT91_PMC_MDIV_4			(3 << 8)



#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */



#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */

#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */

#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */

#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */

#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */

#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */

#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */

#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */

#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */

#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */

#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */

#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */



#endif