Loading arch/arm/mm/cache-feroceon-l2.c +6 −3 Original line number Original line Diff line number Diff line Loading @@ -115,6 +115,10 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end) raw_local_irq_restore(flags); raw_local_irq_restore(flags); } } static inline void l2_inv_all(void) { __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); } /* /* * Linux primitives. * Linux primitives. Loading Loading @@ -254,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) static void __init __invalidate_icache(void) { { int dummy; __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); } } static int __init invalidate_and_disable_icache(void) static int __init invalidate_and_disable_icache(void) Loading Loading @@ -321,6 +323,7 @@ static void __init enable_l2(void) d = flush_and_disable_dcache(); d = flush_and_disable_dcache(); i = invalidate_and_disable_icache(); i = invalidate_and_disable_icache(); l2_inv_all(); write_extra_features(u | 0x00400000); write_extra_features(u | 0x00400000); if (i) if (i) enable_icache(); enable_icache(); Loading Loading
arch/arm/mm/cache-feroceon-l2.c +6 −3 Original line number Original line Diff line number Diff line Loading @@ -115,6 +115,10 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end) raw_local_irq_restore(flags); raw_local_irq_restore(flags); } } static inline void l2_inv_all(void) { __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); } /* /* * Linux primitives. * Linux primitives. Loading Loading @@ -254,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) static void __init __invalidate_icache(void) { { int dummy; __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); } } static int __init invalidate_and_disable_icache(void) static int __init invalidate_and_disable_icache(void) Loading Loading @@ -321,6 +323,7 @@ static void __init enable_l2(void) d = flush_and_disable_dcache(); d = flush_and_disable_dcache(); i = invalidate_and_disable_icache(); i = invalidate_and_disable_icache(); l2_inv_all(); write_extra_features(u | 0x00400000); write_extra_features(u | 0x00400000); if (i) if (i) enable_icache(); enable_icache(); Loading