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Commit f000328a authored by Nicolas Pitre's avatar Nicolas Pitre
Browse files

[ARM] Kirkwood: small L2 code cleanup 



Strictly speaking, a MCR instruction does not produce any output.

Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent d75de087

arch/arm/mm/cache-feroceon-l2.c

+1 −3
Original line number Diff line number Diff line
@@ -258,9 +258,7 @@ static void __init enable_dcache(void) 


static void __init __invalidate_icache(void)

{

	int dummy;



	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy));

	__asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));

}



static int __init invalidate_and_disable_icache(void)