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Commit 4b2c71ed authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gp102-: setup stencil zbc 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e9d03335

drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h

+3 −0
Original line number Diff line number Diff line
@@ -21,12 +21,14 @@ struct nvkm_ltc { 
	int zbc_max;

	u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];

	u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];

	u32 zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];

};



void nvkm_ltc_tags_clear(struct nvkm_device *, u32 first, u32 count);



int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]);

int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32);

int nvkm_ltc_zbc_stencil_get(struct nvkm_ltc *, int index, const u32);



void nvkm_ltc_invalidate(struct nvkm_ltc *);

void nvkm_ltc_flush(struct nvkm_ltc *);
@@ -37,4 +39,5 @@ int gk20a_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); 
int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);

int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);

int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);

int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+6 −6
Original line number Diff line number Diff line
@@ -2204,7 +2204,7 @@ nv132_chipset = { 
	.i2c = gm200_i2c_new,

	.ibus = gm200_ibus_new,

	.imem = nv50_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp100_mc_new,

	.mmu = gp100_mmu_new,

	.therm = gp100_therm_new,
@@ -2240,7 +2240,7 @@ nv134_chipset = { 
	.i2c = gm200_i2c_new,

	.ibus = gm200_ibus_new,

	.imem = nv50_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp100_mc_new,

	.mmu = gp100_mmu_new,

	.therm = gp100_therm_new,
@@ -2276,7 +2276,7 @@ nv136_chipset = { 
	.i2c = gm200_i2c_new,

	.ibus = gm200_ibus_new,

	.imem = nv50_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp100_mc_new,

	.mmu = gp100_mmu_new,

	.therm = gp100_therm_new,
@@ -2312,7 +2312,7 @@ nv137_chipset = { 
	.i2c = gm200_i2c_new,

	.ibus = gm200_ibus_new,

	.imem = nv50_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp100_mc_new,

	.mmu = gp100_mmu_new,

	.therm = gp100_therm_new,
@@ -2348,7 +2348,7 @@ nv138_chipset = { 
	.i2c = gm200_i2c_new,

	.ibus = gm200_ibus_new,

	.imem = nv50_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp100_mc_new,

	.mmu = gp100_mmu_new,

	.therm = gp100_therm_new,
@@ -2380,7 +2380,7 @@ nv13b_chipset = { 
	.fuse = gm107_fuse_new,

	.ibus = gp10b_ibus_new,

	.imem = gk20a_instmem_new,

	.ltc = gp100_ltc_new,

	.ltc = gp102_ltc_new,

	.mc = gp10b_mc_new,

	.mmu = gp10b_mmu_new,

	.secboot = gp10b_secboot_new,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+11 −1
Original line number Diff line number Diff line
@@ -750,7 +750,7 @@ gf100_gr_zbc_init(struct gf100_gr *gr) 
	const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,

			      0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };

	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;

	int index, c = ltc->zbc_min, d = ltc->zbc_min;

	int index, c = ltc->zbc_min, d = ltc->zbc_min, s = ltc->zbc_min;



	if (!gr->zbc_color[0].format) {

		gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]); c++;
@@ -759,12 +759,22 @@ gf100_gr_zbc_init(struct gf100_gr *gr) 
		gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]); c++;

		gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;

		gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;

		if (gr->func->zbc->stencil_get) {

			gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++;

			gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++;

			gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++;

		}

	}



	for (index = c; index <= ltc->zbc_max; index++)

		gr->func->zbc->clear_color(gr, index);

	for (index = d; index <= ltc->zbc_max; index++)

		gr->func->zbc->clear_depth(gr, index);



	if (gr->func->zbc->clear_stencil) {

		for (index = s; index <= ltc->zbc_max; index++)

			gr->func->zbc->clear_stencil(gr, index);

	}

}



/**

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+11 −1
Original line number Diff line number Diff line
@@ -72,6 +72,12 @@ struct gf100_gr_zbc_depth { 
	u32 l2;

};



struct gf100_gr_zbc_stencil {

	u32 format;

	u32 ds;

	u32 l2;

};



struct gf100_gr {

	const struct gf100_gr_func *func;

	struct nvkm_gr base;
@@ -95,6 +101,7 @@ struct gf100_gr { 


	struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];

	struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];

	struct gf100_gr_zbc_stencil zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];



	u8 rop_nr;

	u8 gpc_nr;
@@ -132,6 +139,9 @@ void *gf100_gr_dtor(struct nvkm_gr *); 
struct gf100_gr_func_zbc {

	void (*clear_color)(struct gf100_gr *, int zbc);

	void (*clear_depth)(struct gf100_gr *, int zbc);

	int (*stencil_get)(struct gf100_gr *, int format,

			   const u32 ds, const u32 l2);

	void (*clear_stencil)(struct gf100_gr *, int zbc);

};



struct gf100_gr_func {
@@ -219,11 +229,11 @@ void gm200_gr_init_ds_hww_esr_2(struct gf100_gr *); 
void gp100_gr_init_rop_active_fbps(struct gf100_gr *);

void gp100_gr_init_fecs_exceptions(struct gf100_gr *);

void gp100_gr_init_shader_exceptions(struct gf100_gr *, int, int);

extern const struct gf100_gr_func_zbc gp100_gr_zbc;

void gp100_gr_zbc_clear_color(struct gf100_gr *, int);

void gp100_gr_zbc_clear_depth(struct gf100_gr *, int);



void gp102_gr_init_swdx_pes_mask(struct gf100_gr *);

extern const struct gf100_gr_func_zbc gp102_gr_zbc;



#define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object)

#include <core/object.h>

drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 
			  gr->zbc_depth[zbc].format << ((znum % 4) * 7));

}



const struct gf100_gr_func_zbc

static const struct gf100_gr_func_zbc

gp100_gr_zbc = {

	.clear_color = gp100_gr_zbc_clear_color,

	.clear_depth = gp100_gr_zbc_clear_depth,